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* Remove some DOS line endings accidentially introduced in r3014.Carl-Daniel Hailfinger2008-01-081-11/+11
| | | | | | | | | | No code lines affected, so svn blame will not be messed up. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Initial AMD Barcelona support for rev Bx.Marc Jones2007-12-1921-30/+3695
| | | | | | | | | | | | These are the core files for HyperTransport, DDR2 Memory, and multi-core initialization. Signed-off-by: Marc Jones <marc.jones@amd.com> Reviewed-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Myles Watson <myles@pel.cs.byu.edu> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Whitespace and other code cleanup in peperation for AMD Barcelona support.Marc Jones2007-12-192-210/+206
| | | | | | | | | | Signed-off-by: Marc Jones <marc.jones@amd.com> Reviewed-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Myles Watson <myles@pel.cs.byu.edu> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Update AMD CPU IDs in model_fxx_init.c with information fromUwe Hermann2007-11-291-32/+34
| | | | | | | | | | | | | | the latest version (Rev. 3.73, October 2007) of the 'Revision Guide for AMD Athlon 64 and AMD Opteron Processors' datasheet. Also, add information about the CPU socket for each ID (as per datasheet). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use the preferred order of 'static const' instead of 'const static'.Uwe Hermann2007-10-311-1/+1
| | | | | | | | | | | | | This is the common style in both Linux as well as in LinuxBIOS. Self-ack as this is pretty trivial and a similar patch was already acked. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This code gets us to a working linux boot on the alix1c. I have not tested Ronald G. Minnich2007-10-261-1/+18
| | | | | | | | | | | | | | | | | | | | | | Ethernet yet. The fixes are a board-specific fake spd_read_byte, cleaning up comments, and just in general customizing for the 1c. The lxraminit change fixes a bug (&& used instead of ||), adds some debug prints which were VERY useful debugging the alix1c, changes fatal error messages from print_debug to print_emerg, and adds two functions: banner, which just prints out a string with a banner, and hcf, which print an emergency message and then pushes null bytes into the uart forever, just to make sure that no bytes get lost for any reason. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2899 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* analog changes for the cpu_driver structures...Stefan Reinauer2007-10-244-4/+4
| | | | | | | | | | | | make them const before putting them into the read-only segment... (trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Ever wondered where those "setting incorrect section attributes forStefan Reinauer2007-10-241-1/+1
| | | | | | | | | | | | | | | rodata.pci_driver" warnings are coming from? We were packing those structures into a read-only segment, but forgot to mark them const. Despite its size, this is a fairly trivial patch created by a simple search/replace Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Put the print in the right place. This is trivial patch but a veryRonald G. Minnich2007-10-211-0/+1
| | | | | | | | | | | serious issue, so I am self-acking. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for the Athlon64 x2 5000+ CPU.Torsten Duwe2007-08-301-0/+1
| | | | | | | | | | | | A trivial one-liner for the CPU I happen to have. The sales docs said it's a "G1 revision", but the Rev F code works just fine. Signed-off-by: Torsten Duwe <duwe@lst.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use the common LinuxBIOS license header format.Uwe Hermann2007-05-291-11/+23
| | | | | | | | | | Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Sven Kapferer <skapfere@rumms.uni-mannheim.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This patch fixes the processor name string for Rev F. CPUs.Sven Kapferer2007-05-262-85/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | It moves the complete naming functionality to src/cpu/amd/model_fxx/processor_name.c. The current code sets the processor name string twice for Rev. F CPUs. In src/cpu/amd/model_fxx/model_fxx_init.c the function amd_set_name_string_f is called first. Several lines later init_processor_name is called which doesn't recognize newer CPUs and actually programs incorrect values, thus overwriting the previously set CPU name. For example, this resulted in identifying an Opteron 2218 as a Turion processor. This patch removes the amd_set_name_string_f function from src/cpu/amd/model_fxx/model_fxx_init.c and adds support for Rev. F CPUs to src/cpu/amd/model_fxx/processor_name.c as described in the Revision Guide for AMD NPT Family 0Fh Processors, AMD Document ID 33610 Rev 3.00, October 2006. Signed-off-by: Sven Kapferer <skapfere@rumms.uni-mannheim.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add missing license headers, minor cosmetic fixes in existing headers.Uwe Hermann2007-05-222-19/+18
| | | | | | | | | Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add additional CPU device ID:Jeremy Jackson2007-05-201-0/+1
| | | | | | | | | | | | | | | CPU: vendor AMD device 30ff2 CPU: family 0f, model 3f, stepping 02 All I know is this makes it boot when it didn't before, YMMV. Signed-off-by: Jeremy Jackson <jerj@coplanar.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This patch cleans up and clarifies Geode source code comments.Marc Jones2007-05-102-15/+6
| | | | | | | | | Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* indent is by no means as harmless as one might think ;-)Stefan Reinauer2007-05-101-4/+7
| | | | | | | | | | | | trivial fix. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix the indent and whitespace to match LinuxBIOS standardsJordan Crouse2007-05-105-449/+388
| | | | | | | | | Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2650 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This is the final patch to enable the msm800sev to build. This patchRonald G. Minnich2007-05-051-0/+1
| | | | | | | | | | | | | adds a symbol to the model_lx/cache_as_ram.inc, and modifies some files in the mainboard directory. This patch has been tested but there is a remaining problem which I am tracking down. Expect one more patch to "get it all working". Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This patch adds support for the AMD Geode LX CPU. (rediffed)Marc Jones2007-05-046-530/+627
| | | | | | | | | Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add missing license headers to some Geode LX related files.Jordan Crouse2007-05-034-1/+91
| | | | | | | | | | | | | | | | | The following original authors agreed to the license: - Ronald G. Minnich <rminnich@gmail.com> - Indrek Kruusa <indrek.kruusa@artecdesign.ee> - Stefan Reinauer <stepan@coresystems.de> - Andrei Birjukov <andrei.birjukov@artecdesign.ee> Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This is part of the outstanding mcp55 commit from January 18th. It willYinghai Lu2007-04-062-4/+0
| | | | | | | | | | | | | | | | likely break the build, since it is only a small part, but it needs to go in at some point and doing it directory by directory makes things easier. Signed-off-by: Yinghai Lu <yinghai.lu at amd.com> Signed-off-by: Ed Swierk <eswierk at arastra.com> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ward Vandewege <ward at gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This is (most of) the usb2 debug console code ripped out of Yinghai Lu2007-02-281-0/+12
| | | | | | | | | | | | | | | | | | | | Uwe's version of yh_rest_of_patch.patch (13.02.07 - [PATCH] Rest of huge MCP55 patch). I dropped a lot of stuff, like broken indenting, removed copyright messages, and this printk_ram_* stuff (what the heck is this supposed to be) This codebase is really a mess. Further tarball contributions without a _CLEANED UP_ patch will be denied, especially if they are not from an up to date svn tree. Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Change 'ram' to 'RAM' in user-visible output (closes #60).Uwe Hermann2007-01-162-2/+2
| | | | | | | | | Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use the canonical name of the vendors/devices and theUwe Hermann2006-11-056-6/+6
| | | | | | | | | | | same format for all CHIP_NAME() entries in LinuxBIOS (Closes #20). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@linuxbios.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* CONFIG_USE_PRINTK_IN_CAR and ht chain id for HTX support inYinghai Lu2006-10-046-55/+142
| | | | | | | serengeti_cheeatah git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* socket 939Yinghai Lu2006-10-043-0/+19
| | | | git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2437 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* AMD Rev F supportYinghai Lu2006-10-0421-57/+538
| | | | git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* changes for the lx and artecgroup moboIndrek Kruusa2006-09-133-61/+115
| | | | | | | | Signed-off-by: Indrek Kruusa Approved-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* share decompression code.Stefan Reinauer2006-08-162-170/+2
| | | | git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2378 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Changelog:Indrek Kruusa2006-08-031-28/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | * src/cpu/amd/model_lx/model_lx_init.c L2 cache initialization removed (moved to northbridge.c) * src/include/cpu/amd/lxdef.h more checked values * src/northbridge/amd/lx/northbridge.c L2 cache initialization added cpubug() commented out * src/northbridge/amd/lx/raminit.c empty function sdram_set_registers() is in use, don't remove * src/mainboard/artecgroup/dbe61/Config.lb irqmap changes * src/mainboard/artecgroup/dbe61/irq_tables.c tentative changes to irq table (currently not in use) * src/mainboard/artecgroup/dbe61/mainboard.c irq assigned manually to NIC * src/mainboard/artecgroup/dbe61/Options.lb gcc 4.0 is OK * targets/artecgroup/dbe61/Config.lb 64K for VSA is OK at moment Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee> Signed-off-by: Andrei Birjukov <andrei.birjukov@artecdesign.ee> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Geode LX: this patch adds configuration/status/self-test MSR definitionsIndrek Kruusa2006-08-021-1/+29
| | | | | | | | | | | | for L2 cache and fixes wrong P2D defines. This also patch adds L2 cache initialization for Geode LX CPU. Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This patch adds support for the AMD LX cpu. Ron Minnich2006-07-286-0/+1574
| | | | | | | | | | | | | | | There is one global change to pci_ids.h. The rest are changes for LX. I ran abuild and it is ok. Not all artec design changes are included as some of them would adversely affect other mainboards. Indrek will need to test. Signed-off-by: Ron Minnich Signed-off-by: Indrek Kruusa, indrek.kruusa@artecdesign.ee, artec design. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fixes from AMD. Tested to build on rumba and olpc, and builds. Ronald G. Minnich2006-06-201-110/+95
| | | | | | | Tested to booting linux on olpc, and boots. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2327 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* * delete two empty filesStefan Reinauer2006-06-183-1/+6
| | | | | | | * commit SMM lock code. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* add k8 processor name handling as required by the k8 revision guide.Stefan Reinauer2006-06-143-0/+195
| | | | git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* remove erroneous cache disable.Ronald G. Minnich2006-06-141-3/+11
| | | | git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* changes from AMD for making OLPC video work.Ronald G. Minnich2006-06-103-29/+67
| | | | git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* further development of OLPC. Set vsm size to 35k. add PCI IRQ for USB. Ronald G. Minnich2006-06-081-1/+1
| | | | | | | | Set linuxbios size to 28k. Drop debug level to 8. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* add DK8HTX support. Ronald G. Minnich2006-05-251-2/+94
| | | | | | | VSAs now required to be nrv2 compressed git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2312 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* cleanup some of the compressed rom stream ugliness -- more to do!Ronald G. Minnich2006-05-181-2/+2
| | | | | | | | olpc and rumba can now boot linux out of flash. vsa was resized to 64K. olpc and rumba now used compressed payload -- thanks stefan! git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use a real variable to configure rom base for vsa ...Ronald G. Minnich2006-05-061-1/+3
| | | | git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* fix the treeStefan Reinauer2006-05-041-5/+3
| | | | git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2296 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* core range and set_init_ram_accessYinghai Lu2006-05-042-54/+25
| | | | git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2294 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* rm unused fileYinghai Lu2006-05-041-111/+0
| | | | git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* merge zrom to rom_stream and print olen ilenYinghai Lu2006-05-042-11/+14
| | | | git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2292 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* oops! Slap me on the head for this one. Quick fix for ward untilStefan Reinauer2006-05-031-2/+2
| | | | | | | YhLu's suggestions are all there.. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2291 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* add automatic payload compression method to LinuxBIOSStefan Reinauer2006-05-021-65/+4
| | | | git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fall back to pre-broken settings and setup for GX2. Ronald G. Minnich2006-05-023-101/+124
| | | | | | | We lost a few things, but this is still worth it. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* code cleanup, comments addedLi-Ta Lo2006-04-273-124/+101
| | | | git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2284 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* boot to kernelLi-Ta Lo2006-04-203-72/+17
| | | | git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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