boot to kernel

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 17 insertions, 72 deletions

diff --git a/src/cpu/amd/model_gx2/cpureginit.c b/src/cpu/amd/model_gx2/cpureginit.c
index 51fbe2a..f2802b6 100644
--- a/src/cpu/amd/model_gx2/cpureginit.c
+++ b/src/cpu/amd/model_gx2/cpureginit.c
@@ -169,7 +169,7 @@ cpuRegInit (void){
 /* */
 /*  FooGlue Setup*/
 /* */
-#if 0
+#if 1
 	/*  Enable CIS mode B in FooGlue*/
 	msrnum = MSR_FG + 0x10;
 	msr = rdmsr(msrnum);
diff --git a/src/cpu/amd/model_gx2/model_gx2_init.c b/src/cpu/amd/model_gx2/model_gx2_init.c
index 9fc5d26..c6ad683 100644
--- a/src/cpu/amd/model_gx2/model_gx2_init.c
+++ b/src/cpu/amd/model_gx2/model_gx2_init.c
@@ -6,88 +6,29 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/cache.h>
 
-#if 0
-#include <cpu/amd/gx2def.h>
-#include <arch/io.h>
 
-static void gx2_cpu_setup(void)
+static void vsm_end_post_smi(void)
 {
-	unsigned char rreg;
-	unsigned char cpu_table[] = {
-		0xc1, 0x00,		/* NO SMIs */
-		0xc3, 0x14,		/* Enable CPU config register */
-		0x20, 0x00,		/* */
-		0xb8, GX_BASE>>30,	/* Enable GXBASE address */
-		0xc2, 0x00,
-		0xe8, 0x98,
-		0xc3, 0xf8,		/* Enable CPU config register */
-		0x00, 0x00
-		};
-	unsigned char *cPtr = cpu_table;
-
-	while(rreg = *cPtr++) {
-		unsigned char rval = *cPtr++;
-		outb(rreg, 0x22);
-		outb(rval, 0x23);
-		}
-
-	outb(0xff, 0x22);		/* DIR1 -- Identification register 1 */
-	if(inb(0x23) > 0x63) {		/* Rev greater than R3 */
-		outb(0xe8, 0x22);
-		outb(inb(0x23) | 0x20, 0x23);	/* Enable FPU Fast Mode */
-
-		outb(0xf0, 0x22);
-		outb(inb(0x23) | 0x02, 0x23);	/* Incrementor on */
-
-		outb(0x20, 0x22);
-		outb(inb(0x23) | 0x24, 0x23);	/* Bit 5 must be on */
-						/* Bit 2 Incrementor margin 10 */
-
-	}
-}
-
-static void gx2_gx_setup(void)
-{
-unsigned long gx_setup_table[] = {
-	GX_BASE + DC_UNLOCK, 		DC_UNLOCK_MAGIC,
-	GX_BASE + DC_GENERAL_CFG, 		0,
-	GX_BASE + DC_UNLOCK, 		0,
-	GX_BASE + BC_DRAM_TOP, 		0x3fffffff,
-	GX_BASE + BC_XMAP_1, 		0x60,
-	GX_BASE + BC_XMAP_2, 		0,
-	GX_BASE + BC_XMAP_3, 		0,
-	GX_BASE + MC_BANK_CFG, 		0x00700070,
-	GX_BASE + MC_MEM_CNTRL1, 	XBUSARB,
-	GX_BASE + MC_GBASE_ADD, 	0xff,
-	0, 				0
-	};
-
-unsigned long *gxPtr = gx_setup_table;
-unsigned long *gxdPtr;
-unsigned long addr;
-
-	while(addr = *gxPtr++) {
-		gxdPtr = (unsigned long *)addr;
-		*gxdPtr = *gxPtr++;
-	}
+	__asm__ volatile (
+			  "push %ax\n"
+			  "mov $0x5000, %ax\n"
+			  ".byte 0x0f, 0x38\n"
+			  "pop %ax\n"
+			  );
 }
-#endif
 
 static void model_gx2_init(device_t dev)
 {
-	void do_vsmbios(void);
-#if 0
-	gx2_cpu_setup();
-	gx2_gx_setup();
-#endif
 	printk_debug("model_gx2_init\n");
+
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
 
 	/* Enable the local cpu apics */
-	setup_lapic();
+	//setup_lapic();
+
+	vsm_end_post_smi();
 
-	do_vsmbios();
 	printk_debug("model_gx2_init DONE\n");
 };
 
@@ -96,7 +37,7 @@ static struct device_operations cpu_dev_ops = {
 };
 
 static struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_CYRIX, 0x0540 },
+	{ X86_VENDOR_NSC, 0x0552 },
 	{ 0, 0 },
 };
 
diff --git a/src/cpu/amd/model_gx2/vsmsetup.c b/src/cpu/amd/model_gx2/vsmsetup.c
index b462fcd..3f65774 100644
--- a/src/cpu/amd/model_gx2/vsmsetup.c
+++ b/src/cpu/amd/model_gx2/vsmsetup.c
@@ -283,6 +283,10 @@ void do_vsmbios(void)
 	/* ecx gets smm, edx gets sysm */
 	printk_err("Call real_mode_switch_call_vsm\n");
 	real_mode_switch_call_vsm(0x10000026, 0x10000028);
+
+	/* restart timer 1 */
+	outb(0x56, 0x43);
+	outb(0x12, 0x41);
 }