| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Remove empty lines at end of file | Elyes HAOUAS | 2015-06-08 | 4 | -5/+0 |
| * | Remove address from GPLv2 headers | Patrick Georgi | 2015-05-21 | 5 | -5/+5 |
| * | Unify byte order macros and clrsetbits | Julius Werner | 2015-04-21 | 1 | -21/+0 |
| * | New mechanism to define SRAM/memory map with automatic bounds checking | Julius Werner | 2015-04-06 | 3 | -1/+65 |
| * | src/arch/*/include/stdint.h: Provide definitions for bool type | Alexandru Gagniuc | 2015-02-02 | 1 | -0/+3 |
| * | CBMEM: Tidy up CAR migration | Kyösti Mälkki | 2015-01-27 | 1 | -5/+0 |
| * | CBMEM console: Fix CAR migration step | Kyösti Mälkki | 2015-01-27 | 1 | -0/+1 |
| * | Add UCB RISCV support for architecture, soc, and emulation mainboard.. | Ronald G. Minnich | 2014-12-01 | 11 | -0/+1102 |
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index : coreboot-staging | |
| Partial non-authoritative staging tree (partial copy of Raptor Engineering's internal coreboot staging tree) Don't use unless Gerrit is malfunctioning or down! https://www.raptorengineering.com | Raptor Engineering, LLC |
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