| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Remove address from GPLv2 headers | Patrick Georgi | 2015-05-21 | 1 | -2/+1 |
| * | riscv: use new-style CBFS header lookup | Patrick Georgi | 2015-04-18 | 1 | -19/+0 |
| * | New mechanism to define SRAM/memory map with automatic bounds checking | Julius Werner | 2015-04-06 | 1 | -1/+1 |
| * | Add UCB RISCV support for architecture, soc, and emulation mainboard.. | Ronald G. Minnich | 2014-12-01 | 1 | -0/+104 |
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index : coreboot-staging | |
| Partial non-authoritative staging tree (partial copy of Raptor Engineering's internal coreboot staging tree) Don't use unless Gerrit is malfunctioning or down! https://www.raptorengineering.com | Raptor Engineering, LLC |
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