coreboot-staging - Partial non-authoritative staging tree (partial copy of Raptor Engineering's internal coreboot staging tree) Don't use unless Gerrit is malfunctioning or down! https://www.raptorengineering.com

	Commit message (Expand)	Author	Age	Files	Lines
*	Remove address from GPLv2 headers	Patrick Georgi	2015-05-21	1	-1/+1
*	build system: use archives, not linker action to shorten command lines	Patrick Georgi	2015-05-20	1	-3/+3
*	CBFS: Automate ROM image layout and remove hardcoded offsets	Julius Werner	2015-04-14	1	-1/+1
*	CBFS: Correct ROM_SIZE for ARM boards, use CBFS_SIZE for cbfstool	Julius Werner	2015-04-14	1	-1/+1
*	New mechanism to define SRAM/memory map with automatic bounds checking	Julius Werner	2015-04-06	1	-12/+6
*	build system: run linker scripts through the preprocessor	Patrick Georgi	2015-04-06	1	-10/+14
*	build system x86: deprecate bootblock_lds and ldscripts variables	Patrick Georgi	2015-04-04	1	-1/+1
*	program loading: add prog_run() function	Aaron Durbin	2015-04-03	1	-0/+2
*	RISCV: one last little nit to make it build and run	Ronald G. Minnich	2014-12-05	1	-1/+3
*	RISCV: get RISCV to build again	Ronald G. Minnich	2014-12-04	1	-3/+1
*	Add UCB RISCV support for architecture, soc, and emulation mainboard..	Ronald G. Minnich	2014-12-01	1	-0/+113