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path: root/payloads/libpayload/drivers/timer
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* purin: add basic set of files for libpayloadDaisuke Nojiri2015-04-171-0/+29
| | | | | | | | | | | | | | | | | BUG=none BRANCH=tot TEST=emerge-purin libpayload depthcharge coreboot chromeos-bootimage Change-Id: I6a46067a288ecea352a2724c62c62066e3f4a383 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 355371317dde0546fbab2cd109bc17463f77c4fd Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I8c43acc4d270c3b2d7c18af07c077a553e3c6f6f Original-Reviewed-on: https://chromium-review.googlesource.com/245492 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9753 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* pistachio: modify timer to account for CPU counter overflowIonela Voinescu2015-04-141-1/+12
| | | | | | | | | | | | | | | | | | | | | | | Extended the 32bit CPU counter to 64bit by adding a static variable that takes into account CPU counter overflow. The varibale is updated everythime the timer_raw_value function is called so I assume that the function is called often enought to not miss an overflow of the CPU counter. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; works as expected BRANCH=none Change-Id: I98bcc56e600dcff0c6da7c140dd34faec5e00885 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 972b105f950d800fa44f27bce090f6b89a5a84b9 Original-Change-Id: Id67b14e9d9c2354bc417b6587b615d466690c9b7 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/247642 Original-Reviewed-by: Daniel Ehrenberg <dehrenberg@chromium.org> Reviewed-on: http://review.coreboot.org/9672 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* libpayload: Add drivers for bg4cdDaisuke Nojiri2015-04-081-0/+30
| | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:32772 BRANCH=none TEST=Built chromeos-bootimage Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I15cb40532855c89f6fb959652a7e874897eb45bb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8f8419fe22cf39d827e566b8f4dbe0680e4106a1 Original-Change-Id: I97f2ac8ffc7232c7a6c6d40deb8a35630d3d62a7 Original-Reviewed-on: https://chromium-review.googlesource.com/222662 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9360 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: pistachio: fix timer implementationIonela Voinescu2015-03-211-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | timer_raw_value must return the number of CPU ticks, and not the time obtained by dividing the ticks by the CPU frequency. The CPU counter is increased at every 2 CPU clocks and therfore the number of ticks will be the counter value multiplied by 2. BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA; it works properly. BRANCH=none Change-Id: Iae62cb328e882f84822250bdf72146321ca9bbe0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7ab25ce7dcaffb453ee774d870963a56444d46af Original-Change-Id: I74408950900463a2c054d5aebd3edb005a325adb Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/242393 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8744 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: arch/mips: Add basic MIPS architecture supportIonela Voinescu2015-03-211-0/+36
| | | | | | | | | | | | | | | | | | | | | | Add the basic build infrastructure and architectural support required to build for targets using the MIPS architecture. This will require the addition of cache maintenance. BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA with Depthcharge as payload; successfully executed payload. BRANCH=none Change-Id: I75cfd0536860b6d84b53a567940fe6668d9b2cbb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 758c8cb9a6846e6ca32be409ec5f7a888ac9c888 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Change-Id: I0b9af983bf5032335a519ce2510a0b3aca082edf Original-Reviewed-on: https://chromium-review.googlesource.com/219740 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8741 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* libpayload: Add Rock Chip drivershuang lin2015-01-121-0/+46
| | | | | | | | | | | | | | | | | | | | | | | Add support: 1)Support driver rktimer 2)Support driver rkserial BUG=chrome-os-partner:29778 TEST=emerge-veyron libpayload Original-Change-Id: I2cccedf3b62883dd372842a7972e93f2ebbfb282 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206184 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> (cherry picked from commit 387450d7c36b201bd177d46eb9f1d280fc043aab) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia6b7a8ee2439a6f2bf7577df822d3f4f3a1e441c Reviewed-on: http://review.coreboot.org/8127 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
* ipq8064: Add work around for slow timer clockVadim Bendebury2015-01-041-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | Libpayload libc requires timer clock frequency to be at least 1MHz. Ipq8064 code presently provides a single option of 32kHz. Pretend to be running at 1 MHz without additional accuracy. This is a hack which will be reverted as soon as the SOC is configured to supply a faster running clock. BUG=chrome-os-partner:27784, chrome-os-partner:28880 TEST=with other changes depthcharge boots to the CLI console Original-Change-Id: I80ec6652bc5693a549668cd6e824e9cf5c26b182 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201342 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 466a59967b13986099106f8b44924648c1e6e6cd) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I113689191db70710e7a45ccd02d672f482343e35 Reviewed-on: http://review.coreboot.org/8004 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
* libpayload: ipq8064: Add rudimentary timer driverVadim Bendebury2015-01-041-0/+41
| | | | | | | | | | | | | | | | | | | | | | This is still using the 32kHz timer coreboot uses. A finer granularity timer implementation for 806x is in the works. BUG=chrome-os-partner:27784,chrome-os-partner:28880 TEST=none yet. Original-Change-Id: Iae206749000d45040090df48199c8d86d76bbae5 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/198021 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 8f49f752ab8f84b7c5dc189238732360e8d2aae2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia150c974e5b66939de0b007cf7c1308c187f3289 Reviewed-on: http://review.coreboot.org/8002 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* libpayload: timer: Move the timer drivers from depthcharge to libpayload.Gabe Black2014-11-133-0/+202
These drivers are needed right away and never really fit into depthcharge's driver model anyway. CQ-DEPEND=CL:194064 BUG=None TEST=Built and booted nyan, link, and peach_pit and verified that timer values in cbmem were reasonable. Built for nyan_big, nyan_blaze and daisy. BRANCH=None Original-Change-Id: Ia7953cfece57524262a6c7d6537082af7a00f4d6 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/194058 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit f30a410f0a248c93bc34f5868af1596bf8ce3cdd) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I782d20f3cd63210a87c712643c7a53753f5ef301 Reviewed-on: http://review.coreboot.org/7225 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
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