diff options
Diffstat (limited to 'src/southbridge')
26 files changed, 365 insertions, 123 deletions
diff --git a/src/southbridge/amd/amd8111/amd8111_lpc.c b/src/southbridge/amd/amd8111/amd8111_lpc.c index 802f3c1..c239f7e 100644 --- a/src/southbridge/amd/amd8111/amd8111_lpc.c +++ b/src/southbridge/amd/amd8111/amd8111_lpc.c @@ -162,15 +162,26 @@ static void amd8111_lpc_read_resources(device_t dev) { struct resource *res; - /* Get the normal pci resources of this device */ + /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); - /* Add an extra subtractive resource for both memory and I/O */ + /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void amd8111_lpc_enable_resources(device_t dev) diff --git a/src/southbridge/amd/amd8131/amd8131_bridge.c b/src/southbridge/amd/amd8131/amd8131_bridge.c index 9d85077..29713a3 100644 --- a/src/southbridge/amd/amd8131/amd8131_bridge.c +++ b/src/southbridge/amd/amd8131/amd8131_bridge.c @@ -364,9 +364,6 @@ static void bridge_set_resources(struct device *dev) /* set the memory range */ dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; res->flags |= IORESOURCE_STORED; - compute_allocate_resource(&dev->link[0], res, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM); base = res->base; end = resource_end(res); pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16); diff --git a/src/southbridge/amd/amd8132/amd8132_bridge.c b/src/southbridge/amd/amd8132/amd8132_bridge.c index 12ef26c..8dc57d4 100644 --- a/src/southbridge/amd/amd8132/amd8132_bridge.c +++ b/src/southbridge/amd/amd8132/amd8132_bridge.c @@ -350,9 +350,6 @@ static void bridge_set_resources(struct device *dev) /* set the memory range */ dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; res->flags |= IORESOURCE_STORED; - compute_allocate_resource(&dev->link[0], res, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM); base = res->base; end = resource_end(res); pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16); diff --git a/src/southbridge/amd/cs5530/cs5530_isa.c b/src/southbridge/amd/cs5530/cs5530_isa.c index 3d41d52..a4d3b2e 100644 --- a/src/southbridge/amd/cs5530/cs5530_isa.c +++ b/src/southbridge/amd/cs5530/cs5530_isa.c @@ -25,6 +25,24 @@ #include <device/pci_ids.h> #include "cs5530.h" +static void cs5530_read_resources(device_t dev) +{ + struct resource* res; + + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x400UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + static void isa_init(struct device *dev) { uint8_t reg8; @@ -45,7 +63,7 @@ static void cs5530_pci_dev_enable_resources(device_t dev) } static struct device_operations isa_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = cs5530_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = cs5530_pci_dev_enable_resources, .init = isa_init, diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c index d1ec056..6f351ec 100644 --- a/src/southbridge/amd/cs5535/cs5535.c +++ b/src/southbridge/amd/cs5535/cs5535.c @@ -69,6 +69,24 @@ static void southbridge_enable(struct device *dev) printk_spew("%s: dev is %p\n", __func__, dev); } +static void cs5535_read_resources(device_t dev) +{ + struct resource* res; + + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x400UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + static void cs5535_pci_dev_enable_resources(device_t dev) { printk_spew("cs5535.c: %s()\n", __func__); @@ -77,7 +95,7 @@ static void cs5535_pci_dev_enable_resources(device_t dev) } static struct device_operations southbridge_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = cs5535_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = cs5535_pci_dev_enable_resources, .init = southbridge_init, diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index 4169275..002335d 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -607,6 +607,25 @@ static void southbridge_init(struct device *dev) } } +static void cs5536_read_resources(device_t dev) +{ + struct resource *res; + + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x400UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + static void southbridge_enable(struct device *dev) { printk_err("cs5536: %s: dev is %p\n", __func__, dev); @@ -621,7 +640,7 @@ static void cs5536_pci_dev_enable_resources(device_t dev) } static struct device_operations southbridge_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = cs5536_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = cs5536_pci_dev_enable_resources, .init = southbridge_init, diff --git a/src/southbridge/amd/sb600/sb600_lpc.c b/src/southbridge/amd/sb600/sb600_lpc.c index 50d00e2..b0cff6a 100644 --- a/src/southbridge/amd/sb600/sb600_lpc.c +++ b/src/southbridge/amd/sb600/sb600_lpc.c @@ -70,14 +70,23 @@ static void sb600_lpc_read_resources(device_t dev) pci_get_resource(dev, 0xA0); /* SPI ROM base address */ - /* Add an extra subtractive resource for both memory and I/O */ + /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = - IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = - IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; compact_resources(dev); } @@ -111,7 +120,7 @@ static void sb600_lpc_enable_childrens_resources(device_t dev) for (child = dev->link[link].children; child; child = child->sibling) { enable_resources(child); - if (child->have_resources + if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { for (i = 0; i < child->resources; i++) { struct resource *res; diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c b/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c index c404351..85f9eaf 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c @@ -29,18 +29,27 @@ static void lpc_init(device_t dev) static void bcm5785_lpc_read_resources(device_t dev) { struct resource *res; - unsigned long index; /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); - - /* Add an extra subtractive resource for both memory and I/O */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - + pci_dev_read_resources(dev); + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } /** @@ -69,7 +78,7 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) device_t child; for (child = dev->link[link].children; child; child = child->sibling) { enable_resources(child); - if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) { + if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { for(i=0;i<child->resources;i++) { struct resource *res; unsigned long base, end; // don't need long long diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c b/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c index 8f186f8..34381ea 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c @@ -51,7 +51,6 @@ static void bcm5785_sb_read_resources(device_t dev) /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); - /* Get Resource for SMBUS */ pci_get_resource(dev, 0x90); diff --git a/src/southbridge/intel/esb6300/esb6300_lpc.c b/src/southbridge/intel/esb6300/esb6300_lpc.c index 52db05b..95e888f 100644 --- a/src/southbridge/intel/esb6300/esb6300_lpc.c +++ b/src/southbridge/intel/esb6300/esb6300_lpc.c @@ -361,12 +361,23 @@ static void esb6300_lpc_read_resources(device_t dev) /* Add the GPIO BAR */ res = pci_get_resource(dev, GPIO_BAR); - /* Add an extra subtractive resource for both memory and I/O */ + /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void esb6300_lpc_enable_resources(device_t dev) diff --git a/src/southbridge/intel/i3100/i3100_lpc.c b/src/southbridge/intel/i3100/i3100_lpc.c index f8584ca..a2d858e 100644 --- a/src/southbridge/intel/i3100/i3100_lpc.c +++ b/src/southbridge/intel/i3100/i3100_lpc.c @@ -399,12 +399,23 @@ static void i3100_lpc_read_resources(device_t dev) /* Add the GPIO BAR */ res = pci_get_resource(dev, GPIO_BAR); - /* Add an extra subtractive resource for both memory and I/O */ + /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* Add resource for RCBA */ res = new_resource(dev, RCBA); diff --git a/src/southbridge/intel/i82371eb/i82371eb_isa.c b/src/southbridge/intel/i82371eb/i82371eb_isa.c index dcfa162..a521d86 100644 --- a/src/southbridge/intel/i82371eb/i82371eb_isa.c +++ b/src/southbridge/intel/i82371eb/i82371eb_isa.c @@ -55,8 +55,31 @@ static void isa_init(struct device *dev) isa_dma_init(); } -static const struct device_operations isa_ops = { - .read_resources = pci_dev_read_resources, +static void sb_read_resources(struct device *dev) +{ + struct resource *res; + + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x1000UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 2); + res->base = 0xff800000UL; + res->size = 0x00800000UL; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +const struct device_operations isa_ops = { + .read_resources = sb_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = isa_init, diff --git a/src/southbridge/intel/i82801ca/i82801ca_lpc.c b/src/southbridge/intel/i82801ca/i82801ca_lpc.c index 69535bc..fd16fef 100644 --- a/src/southbridge/intel/i82801ca/i82801ca_lpc.c +++ b/src/southbridge/intel/i82801ca/i82801ca_lpc.c @@ -207,15 +207,26 @@ static void i82801ca_lpc_read_resources(device_t dev) { struct resource *res; - /* Get the normal pci resources of this device */ + /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); - /* Add an extra subtractive resource for both memory and I/O */ + /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void i82801ca_lpc_enable_resources(device_t dev) diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c b/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c index 51debe7..c461673 100644 --- a/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c +++ b/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c @@ -182,15 +182,26 @@ static void i82801dbm_lpc_read_resources(device_t dev) { struct resource *res; - /* Get the normal pci resources of this device */ + /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); - /* Add an extra subtractive resource for both memory and I/O */ + /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void i82801dbm_lpc_enable_resources(device_t dev) diff --git a/src/southbridge/intel/i82801er/i82801er_lpc.c b/src/southbridge/intel/i82801er/i82801er_lpc.c index fa89469..943356c 100644 --- a/src/southbridge/intel/i82801er/i82801er_lpc.c +++ b/src/southbridge/intel/i82801er/i82801er_lpc.c @@ -334,7 +334,7 @@ static void i82801er_lpc_read_resources(device_t dev) { struct resource *res; - /* Get the normal pci resources of this device */ + /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); /* Add the ACPI BAR */ @@ -343,12 +343,23 @@ static void i82801er_lpc_read_resources(device_t dev) /* Add the GPIO BAR */ res = pci_get_resource(dev, GPIO_BAR); - /* Add an extra subtractive resource for both memory and I/O */ + /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void i82801er_lpc_enable_resources(device_t dev) diff --git a/src/southbridge/intel/i82801gx/i82801gx_lpc.c b/src/southbridge/intel/i82801gx/i82801gx_lpc.c index 636b975..73cd29e 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_lpc.c +++ b/src/southbridge/intel/i82801gx/i82801gx_lpc.c @@ -419,12 +419,21 @@ static void i82801gx_lpc_read_resources(device_t dev) /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = - IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = - IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void i82801gx_lpc_enable_resources(device_t dev) diff --git a/src/southbridge/intel/i82801xx/i82801xx_lpc.c b/src/southbridge/intel/i82801xx/i82801xx_lpc.c index cdc809f..f7fae37 100644 --- a/src/southbridge/intel/i82801xx/i82801xx_lpc.c +++ b/src/southbridge/intel/i82801xx/i82801xx_lpc.c @@ -340,12 +340,21 @@ static void i82801xx_lpc_read_resources(device_t dev) /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = - IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = - IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static void i82801xx_lpc_enable_resources(device_t dev) diff --git a/src/southbridge/nvidia/ck804/ck804_lpc.c b/src/southbridge/nvidia/ck804/ck804_lpc.c index bb2cf99..5bdcecd 100644 --- a/src/southbridge/nvidia/ck804/ck804_lpc.c +++ b/src/southbridge/nvidia/ck804/ck804_lpc.c @@ -275,12 +275,21 @@ static void ck804_lpc_read_resources(device_t dev) /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = - IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = - IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } /** @@ -308,7 +317,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) device_t child; for (child = dev->link[link].children; child; child = child->sibling) { enable_resources(child); - if (child->have_resources && (child->path.type == DEVICE_PATH_PNP)) { + if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { for (i = 0; i < child->resources; i++) { struct resource *res; unsigned long base, end; // don't need long long diff --git a/src/southbridge/nvidia/ck804/ck804_pci.c b/src/southbridge/nvidia/ck804/ck804_pci.c index a67eab3..70ccdc6 100644 --- a/src/southbridge/nvidia/ck804/ck804_pci.c +++ b/src/southbridge/nvidia/ck804/ck804_pci.c @@ -5,6 +5,7 @@ #include <console/console.h> #include <device/device.h> +#include <device/resource.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> @@ -13,10 +14,8 @@ static void pci_init(struct device *dev) { uint32_t dword; -#if CONFIG_PCI_64BIT_PREF_MEM == 1 device_t pci_domain_dev; - struct resource *mem1, *mem2; -#endif + struct resource *mem, *pref; dword = pci_read_config32(dev, 0x04); dword |= (1 << 8); /* System error enable */ @@ -36,7 +35,6 @@ static void pci_init(struct device *dev) pci_write_config32(dev, 0x4c, dword); #endif -#if CONFIG_PCI_64BIT_PREF_MEM == 1 pci_domain_dev = dev->bus->dev; while (pci_domain_dev) { if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) @@ -47,21 +45,19 @@ static void pci_init(struct device *dev) if (!pci_domain_dev) return; /* Impossible */ - mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit - mem2 = find_resource(pci_domain_dev, 2); // mem - if (mem1->base > mem2->base) { - dword = mem2->base & (0xffff0000UL); - printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base); + pref = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(2,0)); + mem = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(1,0)); + + if (!mem) + return; /* Impossible */ + + if (!pref || pref->base > mem->base) { + dword = mem->base & (0xffff0000UL); + printk_debug("PCI DOMAIN mem base = 0x%010Lx\n", mem->base); } else { - dword = mem1->base & (0xffff0000UL); - printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n", - mem1->base); + dword = pref->base & (0xffff0000UL); + printk_debug("PCI DOMAIN pref base = 0x%010Lx\n", pref->base); } -#else - dword = dev_root.resource[1].base & (0xffff0000UL); - printk_debug("dev_root mem base = 0x%010Lx\n", - dev_root.resource[1].base); -#endif printk_debug("[0x50] <-- 0x%08x\n", dword); pci_write_config32(dev, 0x50, dword); /* TOM */ diff --git a/src/southbridge/nvidia/mcp55/mcp55_lpc.c b/src/southbridge/nvidia/mcp55/mcp55_lpc.c index 4faaf08..480394e 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_lpc.c +++ b/src/southbridge/nvidia/mcp55/mcp55_lpc.c @@ -248,16 +248,27 @@ static void mcp55_lpc_read_resources(device_t dev) { struct resource *res; - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP + /* Get the normal PCI resources of this device. */ + /* We got one for APIC, or one more for TRAP. */ + pci_dev_read_resources(dev); - /* Add an extra subtractive resource for both memory and I/O */ + /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } /** @@ -265,7 +276,7 @@ static void mcp55_lpc_read_resources(device_t dev) * * @param dev the device whos children's resources are to be enabled * - * This function is call by the global enable_resources() indirectly via the + * This function is called by the global enable_resources() indirectly via the * device_operation::enable_resources() method of devices. * * Indirect mutual recursion: @@ -286,7 +297,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) device_t child; for (child = dev->link[link].children; child; child = child->sibling) { enable_resources(child); - if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) { + if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { for(i=0;i<child->resources;i++) { struct resource *res; unsigned long base, end; // don't need long long diff --git a/src/southbridge/nvidia/mcp55/mcp55_pci.c b/src/southbridge/nvidia/mcp55/mcp55_pci.c index 2ae5a49..3bc3a1a 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_pci.c +++ b/src/southbridge/nvidia/mcp55/mcp55_pci.c @@ -23,6 +23,7 @@ #include <console/console.h> #include <device/device.h> +#include <device/resource.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> @@ -33,10 +34,8 @@ static void pci_init(struct device *dev) uint32_t dword; uint16_t word; -#if CONFIG_PCI_64BIT_PREF_MEM == 1 device_t pci_domain_dev; - struct resource *mem1, *mem2; -#endif + struct resource *mem, *pref; /* System error enable */ dword = pci_read_config32(dev, 0x04); @@ -58,30 +57,32 @@ static void pci_init(struct device *dev) pci_write_config32(dev, 0x4c, dword); #endif -#if CONFIG_PCI_64BIT_PREF_MEM == 1 pci_domain_dev = dev->bus->dev; - while(pci_domain_dev) { - if(pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) break; + while (pci_domain_dev) { + if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) + break; pci_domain_dev = pci_domain_dev->bus->dev; } - if(!pci_domain_dev) return; // impossiable - mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit - mem2 = find_resource(pci_domain_dev, 2); // mem - if(mem1->base > mem2->base) { - dword = mem2->base & (0xffff0000UL); - printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base); + if (!pci_domain_dev) + return; /* Impossible */ + + pref = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(2,0)); + mem = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(1,0)); + + if (!mem) + return; /* Impossible */ + + if (!pref || pref->base > mem->base) { + dword = mem->base & (0xffff0000UL); + printk_debug("PCI DOMAIN mem base = 0x%010Lx\n", mem->base); } else { - dword = mem1->base & (0xffff0000UL); - printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n", mem1->base); + dword = pref->base & (0xffff0000UL); + printk_debug("PCI DOMAIN pref base = 0x%010Lx\n", pref->base); } -#else - dword = dev_root.resource[1].base & (0xffff0000UL); - printk_debug("dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base); -#endif - printk_debug("[0x50] <-- 0x%08x\n", dword); - pci_write_config32(dev, 0x50, dword); //TOM + printk_debug("[0x50] <-- 0x%08x\n", dword); + pci_write_config32(dev, 0x50, dword); /* TOM */ } static struct pci_operations lops_pci = { diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 990fd17..5d5280d 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -172,7 +172,6 @@ void rl5c476_set_resources(device_t dev) resource = find_resource(dev,1); if( !(resource->flags & IORESOURCE_STORED) ){ resource->flags |= IORESOURCE_STORED ; - compute_allocate_resource(&dev->link[0],resource,resource->flags,resource->flags); printk_debug("%s 1 ==> %x\n",dev_path(dev),resource->base); cf_base = resource->base; } diff --git a/src/southbridge/sis/sis966/sis966_lpc.c b/src/southbridge/sis/sis966/sis966_lpc.c index 6d3dd8e..c6762a9 100644 --- a/src/southbridge/sis/sis966/sis966_lpc.c +++ b/src/southbridge/sis/sis966/sis966_lpc.c @@ -239,13 +239,23 @@ static void sis966_lpc_read_resources(device_t dev) /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP - /* Add an extra subtractive resource for both memory and I/O */ + /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } /** @@ -274,7 +284,7 @@ static void sis966_lpc_enable_childrens_resources(device_t dev) device_t child; for (child = dev->link[link].children; child; child = child->sibling) { enable_resources(child); - if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) { + if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { for(i=0;i<child->resources;i++) { struct resource *res; unsigned long base, end; // don't need long long diff --git a/src/southbridge/via/vt8231/vt8231_lpc.c b/src/southbridge/via/vt8231/vt8231_lpc.c index 4b90635..fb2f29b 100644 --- a/src/southbridge/via/vt8231/vt8231_lpc.c +++ b/src/southbridge/via/vt8231/vt8231_lpc.c @@ -131,6 +131,24 @@ static void vt8231_init(struct device *dev) rtc_init(0); } +void vt8231_read_resources(device_t dev) +{ + struct resource *res; + + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x400UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + static void southbridge_init(struct device *dev) { vt8231_init(dev); @@ -138,7 +156,7 @@ static void southbridge_init(struct device *dev) } static struct device_operations vt8231_lpc_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = vt8231_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = &southbridge_init, diff --git a/src/southbridge/via/vt8235/vt8235_lpc.c b/src/southbridge/via/vt8235/vt8235_lpc.c index 521271d..67f602b 100644 --- a/src/southbridge/via/vt8235/vt8235_lpc.c +++ b/src/southbridge/via/vt8235/vt8235_lpc.c @@ -219,15 +219,22 @@ static void vt8235_init(struct device *dev) device has a resource to set - so set a dummy one */ void vt8235_read_resources(device_t dev) { + struct resource *res; - struct resource *resource; pci_dev_read_resources(dev); - resource = new_resource(dev, 1); - resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO | IORESOURCE_STORED; - resource->size = 2; - resource->base = 0x2e; + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x400UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } + void vt8235_set_resources(device_t dev) { struct resource *resource; diff --git a/src/southbridge/winbond/w83c553/w83c553f.c b/src/southbridge/winbond/w83c553/w83c553f.c index 1e17121..8f70ff0 100644 --- a/src/southbridge/winbond/w83c553/w83c553f.c +++ b/src/southbridge/winbond/w83c553/w83c553f.c @@ -188,8 +188,26 @@ static void w83c553_enable_resources(device_t dev) enable_childrens_resources(dev); } +static void w83c553_read_resources(device_t dev) +{ + struct resource* res; + + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x400UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + static struct device_operations w83c553_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = w83c553_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = w83c553_enable_resources, .init = w83c553_init, |