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Diffstat (limited to 'src/soc/nvidia/tegra132/romstage.c')
-rw-r--r-- | src/soc/nvidia/tegra132/romstage.c | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c new file mode 100644 index 0000000..a4a0636 --- /dev/null +++ b/src/soc/nvidia/tegra132/romstage.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/stages.h> +#include <cbfs.h> +#include <console/console.h> +#include <arch/exception.h> + +#include <soc/sdram_configs.h> +#include <soc/nvidia/tegra132/sdram.h> + +void main(void) +{ + void *entry; + + console_init(); + exception_init(); + + printk(BIOS_INFO, "T132: romstage here\n"); + + sdram_init(get_sdram_config()); + + printk(BIOS_INFO, "T132 romstage: sdram_init done\n"); + + while (1); + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); + stage_exit(entry); +} |