diff options
Diffstat (limited to 'src/soc/intel/fsp_baytrail/ramstage.c')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/ramstage.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index e231701..814b16e 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -18,6 +18,7 @@ */ #include <arch/cpu.h> +#include <arch/acpi.h> #include <console/console.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cr.h> @@ -25,10 +26,12 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <romstage_handoff.h> #include <stdlib.h> #include <baytrail/gpio.h> #include <baytrail/lpc.h> +#include <baytrail/nvs.h> #include <baytrail/msr.h> #include <baytrail/pattrs.h> #include <baytrail/pci_devs.h> @@ -123,6 +126,32 @@ static void fill_in_pattrs(void) } +static inline void set_acpi_sleep_type(int val) +{ +#if CONFIG_HAVE_ACPI_RESUME + acpi_slp_type = val; +#endif +} + +static void s3_resume_prepare(void) +{ + global_nvs_t *gnvs; + struct romstage_handoff *romstage_handoff; + + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + + romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { + if (gnvs != NULL) { + memset(gnvs, 0, sizeof(global_nvs_t)); + } + set_acpi_sleep_type(0); + return; + } + + set_acpi_sleep_type(3); +} + void baytrail_init_pre_device(void) { struct soc_gpio_config *config; @@ -132,6 +161,9 @@ void baytrail_init_pre_device(void) /* Allow for SSE instructions to be executed. */ write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); + /* Indicate S3 resume to rest of ramstage. */ + s3_resume_prepare(); + /* Get GPIO initial states from mainboard */ config = mainboard_get_gpios(); setup_soc_gpios(config); |
