15 files changed, 32 insertions, 32 deletions

diff --git a/src/cpu/samsung/exynos5250/clk.h b/src/cpu/samsung/exynos5250/clk.h
index ba8d960..565cf2b 100644
--- a/src/cpu/samsung/exynos5250/clk.h
+++ b/src/cpu/samsung/exynos5250/clk.h
@@ -72,7 +72,7 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral);
 #define MCT_HZ 24000000
 
 /*
- * Set mshci controller instances clock drivder
+ * Set mshci controller instances clock divider
  *
  * @param enum periph_id instance of the mshci controller
  *
@@ -521,7 +521,7 @@ struct exynos5_mct_regs {
 };
 
 #define EXYNOS5_EPLLCON0_LOCKED_SHIFT	29  /* EPLL Locked bit position*/
-#define EPLL_SRC_CLOCK			24000000  /*24 MHz Cristal Input */
+#define EPLL_SRC_CLOCK			24000000  /*24 MHz Crystal Input */
 #define TIMEOUT_EPLL_LOCK		1000
 
 #define AUDIO_0_RATIO_MASK		0x0f
diff --git a/src/cpu/samsung/exynos5250/clock.c b/src/cpu/samsung/exynos5250/clock.c
index 78f0bd4..390fae3 100644
--- a/src/cpu/samsung/exynos5250/clock.c
+++ b/src/cpu/samsung/exynos5250/clock.c
@@ -160,7 +160,7 @@ static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = {
 	{24,	1,	20,	-1}, /* PERIPH_ID_SATA */
 };
 
-/* Epll Clock division values to achive different frequency output */
+/* Epll Clock division values to achieve different frequency output */
 static struct st_epll_con_val epll_div[] = {
 	{ 192000000, 0, 48, 3, 1, 0 },
 	{ 180000000, 0, 45, 3, 1, 0 },
@@ -405,7 +405,7 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor)
 	u32 *reg;
 
 	/*
-	 * For now we only handle a very small subset of peipherals here.
+	 * For now we only handle a very small subset of peripherals here.
 	 * Others will need to (and do) mangle the clock registers
 	 * themselves, At some point it is hoped that this function can work
 	 * from a table or calculated register offset / mask. For now this
@@ -636,7 +636,7 @@ int clock_epll_set_rate(unsigned long rate)
 	epll_con |= epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
 
 	/*
-	 * Required period ( in cycles) to genarate a stable clock output.
+	 * Required period ( in cycles) to generate a stable clock output.
 	 * The maximum clock time can be up to 3000 * PDIV cycles of PLLs
 	 * frequency input (as per spec)
 	 */
@@ -675,7 +675,7 @@ int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
 	unsigned int div ;
 
 	if ((dst_frq == 0) || (src_frq == 0)) {
-		printk(BIOS_DEBUG, "%s: Invalid requency input for prescaler\n", __func__);
+		printk(BIOS_DEBUG, "%s: Invalid frequency input for prescaler\n", __func__);
 		printk(BIOS_DEBUG, "src frq = %d des frq = %d ", src_frq, dst_frq);
 		return -1;
 	}
diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c
index 96e7dc3..61f937b 100644
--- a/src/cpu/samsung/exynos5250/cpu.c
+++ b/src/cpu/samsung/exynos5250/cpu.c
@@ -107,7 +107,7 @@ static void exynos_displayport_init(device_t dev)
 	 *
 	 * Note: We may want to do something clever to ensure the framebuffer
 	 * region is aligned such that we don't change dcache policy for other
-	 * stuff inadvertantly.
+	 * stuff inadvertently.
 	 */
 	uint32_t lower = ALIGN_DOWN(lcdbase, MiB);
 	uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB);
diff --git a/src/cpu/samsung/exynos5250/dmc.h b/src/cpu/samsung/exynos5250/dmc.h
index d676aa7..acd0abb 100644
--- a/src/cpu/samsung/exynos5250/dmc.h
+++ b/src/cpu/samsung/exynos5250/dmc.h
@@ -328,7 +328,7 @@ struct mem_timings {
 	uint8_t chips_per_channel;	/* number of chips per channel */
 	uint8_t chips_to_configure;	/* number of chips to configure */
 	uint8_t send_zq_init;		/* 1 to send this command */
-	unsigned int impedance;		/* drive strength impedeance */
+	unsigned int impedance;		/* drive strength impedance */
 	uint8_t gate_leveling_enable;	/* check gate leveling is enabled */
 };
 
diff --git a/src/cpu/samsung/exynos5250/dmc_common.c b/src/cpu/samsung/exynos5250/dmc_common.c
index 55388ac..b506853 100644
--- a/src/cpu/samsung/exynos5250/dmc_common.c
+++ b/src/cpu/samsung/exynos5250/dmc_common.c
@@ -64,7 +64,7 @@ int dmc_config_zq(struct mem_timings *mem,
 	val &= ~ZQ_MANUAL_STR;
 
 	/*
-	 * Since we are manaully calibrating the ZQ values,
+	 * Since we are manually calibrating the ZQ values,
 	 * we are looping for the ZQ_init to complete.
 	 */
 	i = ZQ_INIT_TIMEOUT;
@@ -97,12 +97,12 @@ void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode)
 		writel(val, &dmc->phycontrol0);
 	}
 
-	/* Update DLL Information: Force DLL Resyncronization */
+	/* Update DLL Information: Force DLL Resynchronization */
 	val = readl(&dmc->phycontrol0);
 	val |= FP_RSYNC;
 	writel(val, &dmc->phycontrol0);
 
-	/* Reset Force DLL Resyncronization */
+	/* Reset Force DLL Resynchronization */
 	val = readl(&dmc->phycontrol0);
 	val &= ~FP_RSYNC;
 	writel(val, &dmc->phycontrol0);
diff --git a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
index cb5c613..554f4c2 100644
--- a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
+++ b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
@@ -139,9 +139,9 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 	writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
 		&dmc->concontrol);
 
-	/* Memory Channel Inteleaving Size */
+	/* Memory Channel Interleaving Size */
 	printk(BIOS_SPEW, "ddr3_mem_ctrl_init: "
-	       "Memory Channel Inteleaving Size\n");
+	       "Memory Channel Interleaving Size\n");
 	writel(mem->iv_size, &dmc->ivcontrol);
 
 	/* Set DMC MEMCONTROL register */
@@ -161,7 +161,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 
 	/* Power Down mode Configuration */
 	printk(BIOS_SPEW, "ddr3_mem_ctrl_init: "
-	       "Power Down mode Configuraation\n");
+	       "Power Down mode Configuration\n");
 	writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
 		mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT,
 		&dmc->pwrdnconfig);
diff --git a/src/cpu/samsung/exynos5250/dp-core.h b/src/cpu/samsung/exynos5250/dp-core.h
index 73f4638..ab7e7e4 100644
--- a/src/cpu/samsung/exynos5250/dp-core.h
+++ b/src/cpu/samsung/exynos5250/dp-core.h
@@ -29,7 +29,7 @@
 #define MAX_CR_LOOP 5
 #define MAX_EQ_LOOP 4
 
-/* Link tare type */
+/* Link rate type */
 enum link_rate {
 	LINK_RATE_1_62GBPS = 0x06,
 	LINK_RATE_2_70GBPS = 0x0a
@@ -126,7 +126,7 @@ struct s5p_dp_device {
  */
 void s5p_dp_reset(struct s5p_dp_device *dp);
 /*
- * Initialize DP to recieve video stream
+ * Initialize DP to receive video stream
  *
  * param dp	pointer to main s5p-dp structure
  */
@@ -214,8 +214,8 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp);
  *
  * param dp		pointer to main s5p-dp structure
  * param type		clock_recovery_m_value_type
- * param m_value	to caluculate m_vid value
- * param n_value	to caluculate n_vid value
+ * param m_value	to calculate m_vid value
+ * param n_value	to calculate n_vid value
  */
 void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp,
 			enum clock_recovery_m_value_type type,
diff --git a/src/cpu/samsung/exynos5250/dp-reg.c b/src/cpu/samsung/exynos5250/dp-reg.c
index eb53356..ac4208d 100644
--- a/src/cpu/samsung/exynos5250/dp-reg.c
+++ b/src/cpu/samsung/exynos5250/dp-reg.c
@@ -91,7 +91,7 @@ void s5p_dp_reset(struct s5p_dp_device *dp)
 	/* Set interrupt pin assertion polarity as high */
 	writel(INT_POL0 | INT_POL1, &base->int_ctl);
 
-	/* Clear pending regisers */
+	/* Clear pending registers */
 	writel(0xff, &base->common_int_sta_1);
 	writel(0x4f, &base->common_int_sta_2);
 	writel(0xe0, &base->common_int_sta_3);
@@ -156,7 +156,7 @@ void s5p_dp_init_aux(struct s5p_dp_device *dp)
 	u32 reg;
 	struct exynos5_dp *base = dp->base;
 
-	/* Clear inerrupts related to AUX channel */
+	/* Clear interrupts related to AUX channel */
 	reg = RPLY_RECEIV | AUX_ERR;
 	writel(reg, &base->dp_int_sta);
 
diff --git a/src/cpu/samsung/exynos5250/fimd.h b/src/cpu/samsung/exynos5250/fimd.h
index 71d1785..f3dea37 100644
--- a/src/cpu/samsung/exynos5250/fimd.h
+++ b/src/cpu/samsung/exynos5250/fimd.h
@@ -86,11 +86,11 @@ struct exynos5_fimd_panel {
 	unsigned int upper_margin;	/* Vertical Backporch */
 	unsigned int lower_margin;	/* Vertical frontporch */
 	unsigned int vsync;		/* Vertical Sync Pulse Width */
-	unsigned int left_margin;	/* Horizantal Backporch */
+	unsigned int left_margin;	/* Horizontal Backporch */
 	unsigned int right_margin;	/* Horizontal Frontporch */
 	unsigned int hsync;		/* Horizontal Sync Pulse Width */
 	unsigned int xres;		/* X Resolution */
-	unsigned int yres;		/* Y Resopultion */
+	unsigned int yres;		/* Y Resolution */
 };
 
 /* LCDIF Register Map */
diff --git a/src/cpu/samsung/exynos5250/pinmux.c b/src/cpu/samsung/exynos5250/pinmux.c
index 1c72353..ab1b25e 100644
--- a/src/cpu/samsung/exynos5250/pinmux.c
+++ b/src/cpu/samsung/exynos5250/pinmux.c
@@ -94,7 +94,7 @@ void exynos_pinmux_sdmmc2(void)
 void exynos_pinmux_sdmmc3(void)
 {
 	/*
-	 * TODO: Need to add defintions for GPC4 before
+	 * TODO: Need to add definitions for GPC4 before
 	 * enabling this.
 	 */
 	printk(BIOS_DEBUG, "SDMMC3 not supported yet");
diff --git a/src/cpu/samsung/exynos5250/setup.h b/src/cpu/samsung/exynos5250/setup.h
index 942a3f1..9f10786 100644
--- a/src/cpu/samsung/exynos5250/setup.h
+++ b/src/cpu/samsung/exynos5250/setup.h
@@ -661,7 +661,7 @@ struct exynos5_phy_control;
 #define MEM_TERM_EN	(1 << 31)	/* Termination enable for memory */
 #define PHY_TERM_EN	(1 << 30)	/* Termination enable for PHY */
 #define DMC_CTRL_SHGATE	(1 << 29)	/* Duration of DQS gating signal */
-#define FP_RSYNC	(1 << 3)	/* Force DLL resyncronization */
+#define FP_RSYNC	(1 << 3)	/* Force DLL resynchronization */
 
 /* Driver strength for CK, CKE, CS & CA */
 #define IMP_OUTPUT_DRV_40_OHM	0x5
@@ -676,7 +676,7 @@ struct exynos5_phy_control;
 
 struct mem_timings;
 
-/* Errors that we can encourter in low-level setup */
+/* Errors that we can encounter in low-level setup */
 enum {
 	SETUP_ERR_OK,
 	SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
diff --git a/src/cpu/samsung/exynos5250/spi.c b/src/cpu/samsung/exynos5250/spi.c
index 642ae23..1c365dc 100644
--- a/src/cpu/samsung/exynos5250/spi.c
+++ b/src/cpu/samsung/exynos5250/spi.c
@@ -42,7 +42,7 @@ static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo,
 	unsigned int *rxp = (unsigned int *)(dinp + (i * (32 * 1024)));
 	unsigned int out_bytes, in_bytes;
 
-	// TODO In currrent implementation, every read/write must be aligned to
+	// TODO In current implementation, every read/write must be aligned to
 	// 4 bytes, otherwise you may get timeout or other unexpected results.
 	ASSERT(todo % 4 == 0);
 
@@ -90,7 +90,7 @@ int exynos_spi_open(struct exynos_spi *regs)
 		     SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
 	clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */
 
-	/* clear rx and tx channel if set priveously */
+	/* clear rx and tx channel if set previously */
 	clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
 
 	setbits_le32(&regs->swap_cfg,
diff --git a/src/cpu/samsung/exynos5250/tmu.c b/src/cpu/samsung/exynos5250/tmu.c
index 5a871fd..1b5e9c2 100644
--- a/src/cpu/samsung/exynos5250/tmu.c
+++ b/src/cpu/samsung/exynos5250/tmu.c
@@ -69,8 +69,8 @@ struct tmu_info exynos5250_tmu_info = {
 
 /*
  * After reading temperature code from register, compensating
- * its value and calculating celsius temperatue,
- * get current temperatue.
+ * its value and calculating celsius temperature,
+ * get current temperature.
  *
  * @return	current temperature of the chip as sensed by TMU
  */
diff --git a/src/cpu/samsung/exynos5250/tmu.h b/src/cpu/samsung/exynos5250/tmu.h
index 03eacd2..bda4bd7 100644
--- a/src/cpu/samsung/exynos5250/tmu.h
+++ b/src/cpu/samsung/exynos5250/tmu.h
@@ -65,7 +65,7 @@ enum tmu_status_t {
 	TMU_STATUS_TRIPPED,
 };
 
-/* Tmeperature threshold values for various thermal events */
+/* Temperature threshold values for various thermal events */
 struct temperature_params {
 	/* minimum value in temperature code range */
 	unsigned int min_val;
diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c
index 41dc709..dbf7202 100644
--- a/src/cpu/samsung/exynos5250/uart.c
+++ b/src/cpu/samsung/exynos5250/uart.c
@@ -37,7 +37,7 @@ static uint32_t base_port = CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
  * The coefficient, used to calculate the baudrate on S5P UARTs is
  * calculated as
  * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
- * however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1,
+ * however, section 31.6.11 of the datasheet doesn't recommend using 1 for 1,
  * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
  */
 static const int udivslot[] = {
@@ -129,7 +129,7 @@ static int exynos5_uart_err_check(int op)
 
 /*
  * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
+ * otherwise. When the function is successful, the character read is
  * written into its argument c.
  */
 static unsigned char exynos5_uart_rx_byte(void)