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-rw-r--r--src/mainboard/amd/inagua/Kconfig4
-rw-r--r--src/mainboard/amd/inagua/romstage.c7
-rw-r--r--src/mainboard/amd/torpedo/Kconfig4
-rw-r--r--src/mainboard/amd/torpedo/romstage.c6
-rw-r--r--src/superio/smsc/kbc1100/Makefile.inc1
-rw-r--r--src/superio/smsc/kbc1100/early_init.c (renamed from src/superio/smsc/kbc1100/kbc1100_early_init.c)36
-rw-r--r--src/superio/smsc/kbc1100/kbc1100.h10
7 files changed, 40 insertions, 28 deletions
diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig
index 1e11f9f..279c7ef 100644
--- a/src/mainboard/amd/inagua/Kconfig
+++ b/src/mainboard/amd/inagua/Kconfig
@@ -69,10 +69,6 @@ config RAMBASE
hex
default 0x200000
-config SIO_PORT
- hex
- default 0x2e
-
config DRIVERS_PS2_KEYBOARD
bool
default y
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index a304d31..a7b8a40 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -33,11 +33,13 @@
#include "cpu/amd/car.h"
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
-#include "superio/smsc/kbc1100/kbc1100_early_init.c"
+#include <superio/smsc/kbc1100/kbc1100.h>
#include "cpu/x86/lapic.h"
#include <sb_cimx.h>
#include "SBPLATFORM.h"
+#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
+
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
@@ -57,7 +59,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb_Poweron_Init();
post_code(0x31);
- kbc1100_early_init(CONFIG_SIO_PORT);
+ kbc1100_early_init(0x2e);
+ kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
}
diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig
index 62ce043..6013df7 100644
--- a/src/mainboard/amd/torpedo/Kconfig
+++ b/src/mainboard/amd/torpedo/Kconfig
@@ -79,10 +79,6 @@ config RAMBASE
hex
default 0x200000
-config SIO_PORT
- hex
- default 0x2e
-
config ONBOARD_VGA_IS_PRIMARY
bool
default y
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index dcab52b..e3416c7 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -30,13 +30,14 @@
#include "cpu/amd/car.h"
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
-#include "superio/smsc/kbc1100/kbc1100_early_init.c"
+#include <superio/smsc/kbc1100/kbc1100.h>
#include "cpu/x86/lapic.h"
#include "sb_cimx.h"
#include "SbPlatform.h"
#include <arch/cpu.h>
#include "platform_cfg.h"
+#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -57,7 +58,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x31);
- kbc1100_early_init(CONFIG_SIO_PORT);
+ kbc1100_early_init(0x2e);
+ kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
post_code(0x32);
post_code(0x33);
diff --git a/src/superio/smsc/kbc1100/Makefile.inc b/src/superio/smsc/kbc1100/Makefile.inc
index 603d24e..c3385a6 100644
--- a/src/superio/smsc/kbc1100/Makefile.inc
+++ b/src/superio/smsc/kbc1100/Makefile.inc
@@ -17,4 +17,5 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
+romstage-$(CONFIG_SUPERIO_SMSC_KBC1100) += early_init.c
ramstage-$(CONFIG_SUPERIO_SMSC_KBC1100) += superio.c
diff --git a/src/superio/smsc/kbc1100/kbc1100_early_init.c b/src/superio/smsc/kbc1100/early_init.c
index 5d74c32..d075f9c 100644
--- a/src/superio/smsc/kbc1100/kbc1100_early_init.c
+++ b/src/superio/smsc/kbc1100/early_init.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -20,40 +21,44 @@
/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */
#include <arch/io.h>
+#include <device/pnp.h>
+#include <stdint.h>
+
#include "kbc1100.h"
-static inline void pnp_enter_conf_state(device_t dev)
+static void pnp_enter_conf_state(device_t dev)
{
- unsigned port = dev>>8;
- outb(0x55, port);
+ u16 port = dev >> 8;
+ outb(0x55, port);
}
static void pnp_exit_conf_state(device_t dev)
{
- unsigned port = dev>>8;
- outb(0xaa, port);
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
+void kbc1100_early_serial(device_t dev, u16 iobase)
+{
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_conf_state(dev);
}
-static inline void kbc1100_early_init(unsigned port)
+void kbc1100_early_init(u16 port)
{
device_t dev;
dev = PNP_DEV (port, KBC1100_KBC);
-
pnp_enter_conf_state(dev);
/* Serial IRQ enabled */
outb(0x25, port);
outb(0x04, port + 1);
- /* Enable SMSC UART 0 */
- dev = PNP_DEV (port, SMSCSUPERIO_SP1);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE);
- pnp_set_enable(dev, 1);
-
/* Enable keyboard */
- dev = PNP_DEV (port, KBC1100_KBC);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
@@ -72,4 +77,3 @@ static inline void kbc1100_early_init(unsigned port)
/* disable the 1s timer */
outb(0xE7, 0x64);
}
-
diff --git a/src/superio/smsc/kbc1100/kbc1100.h b/src/superio/smsc/kbc1100/kbc1100.h
index 3fe6327..2b588f9 100644
--- a/src/superio/smsc/kbc1100/kbc1100.h
+++ b/src/superio/smsc/kbc1100/kbc1100.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,6 +18,12 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#ifndef SUPERIO_SMSC_KBC1100_H
+#define SUPERIO_SMSC_KBC1100_H
+
+#include <arch/io.h>
+#include <stdint.h>
+
#define KBC1100_PM1 1 /* PM1 */
#define SMSCSUPERIO_SP1 4 /* Com1 */
#define SMSCSUPERIO_SP2 5 /* Com2 */
@@ -29,4 +36,7 @@
#define KBC1100_EC1 0x0D /* EC Channel 1 */
#define KBC1100_EC2 0x0E /* EC Channel 2 */
+void kbc1100_early_serial(device_t dev, u16 iobase);
+void kbc1100_early_init(u16 port);
+#endif /* SUPERIO_SMSC_KBC1100_H */
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