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-rw-r--r--payloads/libpayload/arch/arm64/cache.c6
-rw-r--r--payloads/libpayload/include/arm64/arch/cache.h3
2 files changed, 9 insertions, 0 deletions
diff --git a/payloads/libpayload/arch/arm64/cache.c b/payloads/libpayload/arch/arm64/cache.c
index 799e2d2..0755c56 100644
--- a/payloads/libpayload/arch/arm64/cache.c
+++ b/payloads/libpayload/arch/arm64/cache.c
@@ -122,3 +122,9 @@ void cache_sync_instructions(void)
dcache_clean_all(); /* includes trailing DSB (in assembly) */
icache_invalidate_all(); /* includes leading DSB and trailing ISB */
}
+
+void arch_program_segment_loaded(void const *addr, size_t len)
+{
+ dcache_clean_invalidate_by_mva(addr, len);
+ icache_invalidate_all();
+}
diff --git a/payloads/libpayload/include/arm64/arch/cache.h b/payloads/libpayload/include/arm64/arch/cache.h
index 7577758..7248869 100644
--- a/payloads/libpayload/include/arm64/arch/cache.h
+++ b/payloads/libpayload/include/arm64/arch/cache.h
@@ -100,6 +100,9 @@ void dcache_mmu_enable(void);
/* perform all icache/dcache maintenance needed after loading new code */
void cache_sync_instructions(void);
+/* Ensure that loaded program segment is synced back from cache to PoC */
+void arch_program_segment_loaded(void const *addr, size_t len);
+
/* tlb invalidate all */
void tlb_invalidate_all(void);
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