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authorzbao <fishbaozi@gmail.com>2015-12-07 05:17:23 -0500
committerZheng Bao <zheng.bao@amd.com>2015-12-08 03:45:11 +0100
commit85f362e9b6ec69ead84f22d5cf0f5f1995d08b6d (patch)
tree83a01c6717044f5cf085453a079258571c0a06b2 /util
parent6215b88aee845046a73613f1508e6fa779427add (diff)
downloadcoreboot-staging-85f362e9b6ec69ead84f22d5cf0f5f1995d08b6d.zip
coreboot-staging-85f362e9b6ec69ead84f22d5cf0f5f1995d08b6d.tar.gz
amdfwtool: Fill the first 3 romsig entries as 0
I didn't go back through the development guide for this. But based on test, if the empty entry is filled as 0xFFFFFFFF, instead of 0, the USB3 port can not be used. Leave the entries of PSP and PSP2 as 0xFFFFFFFF to be compliant with the case before the amdfwtool is used. Change-Id: Icd5f9891e541279dbd551bbceaf091488d22bfef Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/12665 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'util')
-rw-r--r--util/amdfwtool/amdfwtool.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index f958aba..b08a961 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -377,6 +377,9 @@ int main(int argc, char **argv)
current = AMD_ROMSIG_OFFSET;
amd_romsig = rom + AMD_ROMSIG_OFFSET;
amd_romsig[0] = 0x55AA55AA; /* romsig */
+ amd_romsig[1] = 0;
+ amd_romsig[2] = 0;
+ amd_romsig[3] = 0;
current += 0x20; /* size of ROMSIG */
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