skylake: clean up SMM region calculations

The TSEG is defined to be from TSEG->BGSM in the
host bridge registers. Use those registers at
runtime to calculate the correct TSEG size.

Lastly, use a few helper macros to make constants
more readable.

BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built, booted, suspended, resumed on glados.

Original-Change-Id: I6db424a0057ecfc040a3cd5d99476c2fb8f5d29b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290832
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I6890fa450ce8dc10080321aa1a7580e0adc48ad5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11195
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

2 files changed, 19 insertions, 13 deletions

diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h
index d895302..fbae6ef 100644
--- a/src/soc/intel/skylake/include/soc/smm.h
+++ b/src/soc/intel/skylake/include/soc/smm.h
@@ -51,7 +51,6 @@ struct smm_relocation_params {
 	int smm_save_state_in_msrs;
 };
 
-#define smm_region_size mmap_region_granluarity
 #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
 int smm_initialize(void);
 void smm_relocate(void);
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index bba93cb..81ec89d 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -25,6 +25,7 @@
 #include <soc/romstage.h>
 #include <soc/smm.h>
 #include <soc/systemagent.h>
+#include <stdlib.h>
 
 size_t mmap_region_granluarity(void)
 {
@@ -34,24 +35,30 @@ size_t mmap_region_granluarity(void)
 			return CONFIG_SMM_TSEG_SIZE;
 
 	/* Make it 8MiB by default. */
-	return 8 << 20;
+	return 8*MiB;
 }
 
-static void *smm_region_start(void)
+/* Returns base of requested region encoded in the system agent. */
+static inline uintptr_t system_agent_region_base(size_t reg)
 {
-	/*
-	 * SMM base address matches the top of DPR.  The DPR register has
-	 * 1 MiB alignment and reports the TOP of the DPR range.
-	 */
-	uint32_t smm_base = pci_read_config32(SA_DEV_ROOT, DPR);
-	smm_base = ALIGN_DOWN(smm_base, 1 << 20);
-	return (void *)smm_base;
+	/* All regions concerned for have 1 MiB alignment. */
+	return ALIGN_DOWN(pci_read_config32(SA_DEV_ROOT, reg), 1*MiB);
+}
+
+static inline uintptr_t smm_region_start(void)
+{
+	return system_agent_region_base(TSEG);
+}
+
+static inline size_t smm_region_size(void)
+{
+	return system_agent_region_base(BGSM) - smm_region_start();
 }
 
 void smm_region(void **start, size_t *size)
 {
-	*start = smm_region_start();
-	*size = mmap_region_granluarity();
+	*start = (void *)smm_region_start();
+	*size = smm_region_size();
 }
 
 void *cbmem_top(void)
@@ -84,7 +91,7 @@ void *cbmem_top(void)
 	 *     +-------------------------+
 	 */
 
-	unsigned long top_of_ram = (unsigned long)smm_region_start();
+	uintptr_t top_of_ram = smm_region_start();
 
 	/*
 	 * Subtract DMA Protected Range size if enabled and align to a multiple