diff options
author | Myles Watson <mylesgw@gmail.com> | 2010-09-25 10:42:55 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2010-09-25 10:42:55 +0000 |
commit | 7fd931b11d6727f489f8ed76530b43a382ed3c60 (patch) | |
tree | ab45684a0d852e7aa4a30e40d224342c28e41a28 /src | |
parent | 10ec0fed8e3336d52ab35f8da91a2a9423d3e969 (diff) | |
download | coreboot-staging-7fd931b11d6727f489f8ed76530b43a382ed3c60.zip coreboot-staging-7fd931b11d6727f489f8ed76530b43a382ed3c60.tar.gz |
Keep the mc146818rtc.h include close to the option table include where
possible.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r-- | src/mainboard/dell/s1850/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/intel/jarrell/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dai_g/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dhe_g/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dhe_g2/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dhr_ig/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dhr_ig2/romstage.c | 1 | ||||
-rw-r--r-- | src/northbridge/intel/e7520/raminit.c | 3 | ||||
-rw-r--r-- | src/northbridge/intel/e7525/raminit.c | 1 |
9 files changed, 3 insertions, 8 deletions
diff --git a/src/mainboard/dell/s1850/romstage.c b/src/mainboard/dell/s1850/romstage.c index c2533d7..d96e196 100644 --- a/src/mainboard/dell/s1850/romstage.c +++ b/src/mainboard/dell/s1850/romstage.c @@ -5,7 +5,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c index 1caf4b9..4df85cf 100644 --- a/src/mainboard/intel/jarrell/romstage.c +++ b/src/mainboard/intel/jarrell/romstage.c @@ -5,7 +5,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index bfbb3bc..6f8ea12 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -5,7 +5,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include "lib/ramtest.c" #include "pc80/udelay_io.c" diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index 8151518..745da9a 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -5,7 +5,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include "lib/ramtest.c" #include "pc80/udelay_io.c" diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c index 7f20e0a..6a2b2ea 100644 --- a/src/mainboard/supermicro/x6dhe_g2/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c @@ -5,7 +5,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 1269eb9..9d56f5c 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -5,7 +5,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index 245c03e..a0f6b49 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -5,7 +5,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c index 0ef73cc..e9827c4 100644 --- a/src/northbridge/intel/e7520/raminit.c +++ b/src/northbridge/intel/e7520/raminit.c @@ -23,6 +23,7 @@ #include <stdlib.h> #include "raminit.h" #include "e7520.h" +#include <pc80/mc146818rtc.h> #if CONFIG_HAVE_OPTION_TABLE #include "option_table.h" #endif @@ -626,7 +627,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { ecc = 0; /* ECC off in CMOS so disable it */ print_debug("ECC off\n"); - } else + } else #endif { print_debug("ECC on\n"); diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c index a33b0c7..b482bb9 100644 --- a/src/northbridge/intel/e7525/raminit.c +++ b/src/northbridge/intel/e7525/raminit.c @@ -23,6 +23,7 @@ #include <stdlib.h> #include "raminit.h" #include "e7525.h" +#include <pc80/mc146818rtc.h> #if CONFIG_HAVE_OPTION_TABLE #include "option_table.h" #endif |