t132: Add shared romstage

There's no reason to duplicate code in the mainboards. Therefore,
drive the flow of romstage boot in the SoC. This allows for
easier scaling with multiple devices.

BUG=None
BRANCH=None
TEST=Built and booted to same place as before.

Original-Change-Id: I0d4df84034b19353daad0da1f722b820596c4f55
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205992
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ie74f0eb1c983aff92d3cbafb7fe7d9d7cb65ae19
Reviewed-on: http://review.coreboot.org/8575
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

5 files changed, 10 insertions, 11 deletions

diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc
index 746af11..6f4a774 100644
--- a/src/mainboard/google/rush/Makefile.inc
+++ b/src/mainboard/google/rush/Makefile.inc
@@ -32,8 +32,7 @@ bootblock-y += bootblock.c
 bootblock-y += pmic.c
 bootblock-y += reset.c
 
-romstage-y += romstage.c
 romstage-y += reset.c
 romstage-y += sdram_configs.c
 
-ramstage-y += mainboard.c
\ No newline at end of file
+ramstage-y += mainboard.c
diff --git a/src/mainboard/google/rush/sdram_configs.c b/src/mainboard/google/rush/sdram_configs.c
index 18386ac..ea62499 100644
--- a/src/mainboard/google/rush/sdram_configs.c
+++ b/src/mainboard/google/rush/sdram_configs.c
@@ -18,8 +18,7 @@
  */
 
 #include <console/console.h>
-#include <soc/nvidia/tegra132/sdram.h>
-#include "sdram_configs.h"
+#include <soc/sdram_configs.h>
 
 static struct sdram_params sdram_configs[] = {
 #include "bct/sdram-hynix-2GB-924.inc"			/* ram_code = 0000 */
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index 855ef24..a984674 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -24,6 +24,7 @@ romstage-y += spi.c
 romstage-y += i2c.c
 romstage-y += dma.c
 romstage-y += monotonic_timer.c
+romstage-y += romstage.c
 romstage-y += sdram.c
 romstage-y += sdram_lp0.c
 romstage-y += ../tegra/gpio.c
diff --git a/src/mainboard/google/rush/sdram_configs.h b/src/soc/nvidia/tegra132/include/soc/sdram_configs.h
index e00e9ca..300be10 100644
--- a/src/mainboard/google/rush/sdram_configs.h
+++ b/src/soc/nvidia/tegra132/include/soc/sdram_configs.h
@@ -17,12 +17,12 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#ifndef __MAINBOARD_GOOGLE_RUSH_SDRAM_CONFIG_H__
-#define __MAINBOARD_GOOGLE_RUSH_SDRAM_CONFIG_H__
+#ifndef __SOC_NVIDIA_TEGRA132_SDRAM_CONFIGS_H__
+#define __SOC_NVIDIA_TEGRA132_SDRAM_CONFIGS_H__
 
-#include <soc/nvidia/tegra132/sdram_param.h>
+#include <soc/nvidia/tegra132/sdram.h>
 
 /* Loads SDRAM configurations for current system. */
 const struct sdram_params *get_sdram_config(void);
 
-#endif  /* __MAINBOARD_GOOGLE_RUSH_SDRAM_CONFIG_H__ */
+#endif  /* __SOC_NVIDIA_TEGRA132_SDRAM_CONFIGS_H__ */
diff --git a/src/mainboard/google/rush/romstage.c b/src/soc/nvidia/tegra132/romstage.c
index 9db5298..a4a0636 100644
--- a/src/mainboard/google/rush/romstage.c
+++ b/src/soc/nvidia/tegra132/romstage.c
@@ -22,7 +22,7 @@
 #include <console/console.h>
 #include <arch/exception.h>
 
-#include "sdram_configs.h"
+#include <soc/sdram_configs.h>
 #include <soc/nvidia/tegra132/sdram.h>
 
 void main(void)
@@ -40,6 +40,6 @@ void main(void)
 
 	while (1);
 
-        entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
-        stage_exit(entry);
+	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
+	stage_exit(entry);
 }