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authorRonald G. Minnich <rminnich@gmail.com>2005-10-19 17:35:18 +0000
committerRonald G. Minnich <rminnich@gmail.com>2005-10-19 17:35:18 +0000
commit1cf26a88841765e7b9477e922199476a92ac4fa4 (patch)
treea5d331d8c33018afdb943d3d8fb169faab568b29 /src/superio/NSC/pc87417/superio.c
parent20d943d9f982f777ac7d97bce56367fc4a2e6a95 (diff)
downloadcoreboot-staging-1cf26a88841765e7b9477e922199476a92ac4fa4.zip
coreboot-staging-1cf26a88841765e7b9477e922199476a92ac4fa4.tar.gz
We are adding this obsolete, deprecated part to support the momentum
apache board. We're not filling in all the support, since it appears nobody uses this part. If you really need parallel port support, add it. We hope to remove this part in future if the only board using it moves to a newer part. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/superio/NSC/pc87417/superio.c')
-rw-r--r--src/superio/NSC/pc87417/superio.c77
1 files changed, 77 insertions, 0 deletions
diff --git a/src/superio/NSC/pc87417/superio.c b/src/superio/NSC/pc87417/superio.c
new file mode 100644
index 0000000..2e75f82
--- /dev/null
+++ b/src/superio/NSC/pc87417/superio.c
@@ -0,0 +1,77 @@
+/* Copyright 2000 AG Electronics Ltd. */
+/* Copyright 2003-2004 Linux Networx */
+/* This code is distributed without warranty under the GPL v2 (see COPYING) */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <string.h>
+#include <bitops.h>
+#include "chip.h"
+#include "pc87417.h"
+
+
+static void init(device_t dev)
+{
+ struct superio_NSC_pc87417_config *conf;
+ struct resource *res0, *res1;
+ /* Wishlist handle well known programming interfaces more
+ * generically.
+ */
+ if (!dev->enabled) {
+ return;
+ }
+ conf = dev->chip_info;
+ switch(dev->path.u.pnp.device) {
+ case PC87417_SP1:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ init_uart8250(res0->base, &conf->com1);
+ break;
+ case PC87417_SP2:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ init_uart8250(res0->base, &conf->com2);
+ break;
+ case PC87417_KBCK:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ res1 = find_resource(dev, PNP_IDX_IO1);
+ init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
+ break;
+ }
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = pnp_set_resources,
+ .enable_resources = pnp_enable_resources,
+ .enable = pnp_enable,
+ .init = init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, PC87417_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, },
+ { &ops, PC87417_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, PC87417_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, PC87417_SWC, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0,
+ { 0xfff0, 0 }, { 0xfffc, 0 }, { 0xfffc, 0 }, { 0xfff8, 0 } },
+ { &ops, PC87417_KBCM, PNP_IRQ0 },
+ { &ops, PC87417_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
+ { &ops, PC87417_GPIO, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } },
+ { &ops, PC87417_WDT, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 } },
+ { &ops, PC87417_FMC, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } },
+ { &ops, PC87417_XBUS, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } },
+ { &ops, PC87417_RTC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xfffe, 0 }, { 0xfffe, 0 } },
+ { &ops, PC87417_MHC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xffe0, 0 }, { 0xffe0, 0 } },
+};
+
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &ops,
+ sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+}
+
+struct chip_operations superio_NSC_pc87417_ops = {
+ CHIP_NAME("NSC 87417")
+ .enable_dev = enable_dev,
+};
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