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author | Dave Frodin <dave.frodin@se-eng.com> | 2015-01-27 07:19:48 -0700 |
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committer | Dave Frodin <dave.frodin@se-eng.com> | 2015-02-05 17:33:00 +0100 |
commit | 9cfa742a264442a8796120964b06fcc8e03185bf (patch) | |
tree | 311dea3a9bd784725a4a68992c6428346e926949 /src/southbridge | |
parent | c3f6bb086beeaca831877813589dc298faaa5dbe (diff) | |
download | coreboot-staging-9cfa742a264442a8796120964b06fcc8e03185bf.zip coreboot-staging-9cfa742a264442a8796120964b06fcc8e03185bf.tar.gz |
southbridge/amd/pi: Add the bolton definitions
This adds the PCI and interrupt related definitions
for the bolton specific features.
Change-Id: Ia6530c57ec5a4a5c4525bfbae0eb5db04c0bef9e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8286
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r-- | src/southbridge/amd/pi/hudson/amd_pci_int_defs.h | 19 | ||||
-rw-r--r-- | src/southbridge/amd/pi/hudson/amd_pci_int_types.h | 12 | ||||
-rw-r--r-- | src/southbridge/amd/pi/hudson/pci_devs.h | 30 |
3 files changed, 57 insertions, 4 deletions
diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h index e6bd2da..78a40f0 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h @@ -25,7 +25,6 @@ * into the FCH PCI_INTR 0xC00/0xC01 interrupt * routing table */ -#define FCH_INT_TABLE_SIZE 0x63 #define PIRQ_NC 0x1F /* Not Used */ #define PIRQ_A 0x00 /* INT A */ @@ -41,9 +40,9 @@ #define PIRQ_MISC1 0x0A /* Miscellaneous1 IRQ Settings */ #define PIRQ_MISC2 0x0B /* Miscellaneous2 IRQ Settings */ #define PIRQ_SIRQA 0x0C /* Serial IRQ INTA */ -#define PIRQ_SIRQB 0x0D /* Serial IRQ INTA */ -#define PIRQ_SIRQC 0x0E /* Serial IRQ INTA */ -#define PIRQ_SIRQD 0x0F /* Serial IRQ INTA */ +#define PIRQ_SIRQB 0x0D /* Serial IRQ INTB */ +#define PIRQ_SIRQC 0x0E /* Serial IRQ INTC */ +#define PIRQ_SIRQD 0x0F /* Serial IRQ INTD */ #define PIRQ_SCI 0x10 /* SCI IRQ */ #define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ #define PIRQ_ASF 0x12 /* ASF */ @@ -67,6 +66,18 @@ #define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */ #define PIRQ_IDE 0x40 /* IDE 14h.1 */ #define PIRQ_SATA 0x41 /* SATA 11h.0 */ + +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) +#define FCH_INT_TABLE_SIZE 0x63 #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ +#endif + +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) +#define FCH_INT_TABLE_SIZE 0x54 +#define PIRQ_GPP0 0x50 /* GPP INT 0 */ +#define PIRQ_GPP1 0x51 /* GPP INT 1 */ +#define PIRQ_GPP2 0x52 /* GPP INT 2 */ +#define PIRQ_GPP3 0x53 /* GPP INT 3 */ +#endif #endif /* AMD_PCI_INT_DEFS_H */ diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h index d0fe9c8..517c892 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h @@ -20,6 +20,17 @@ #ifndef AMD_PCI_INT_TYPES_H #define AMD_PCI_INT_TYPES_H +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) +const char * intr_types[] = { + [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", + [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", + [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "SD\t\t", "GEC\t", "PerMon\t", + [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t", + [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC", + [0x40] = "IDE\t", "SATA\t", + [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t" +}; +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) const char * intr_types[] = { [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", @@ -29,5 +40,6 @@ const char * intr_types[] = { [0x40] = "RSVD\t", "SATA\t", [0x60] = "RSVD\t", "RSVD\t", "GPIO\t", }; +#endif #endif /* AMD_PCI_INT_TYPES_H */ diff --git a/src/southbridge/amd/pi/hudson/pci_devs.h b/src/southbridge/amd/pi/hudson/pci_devs.h index d2549d4..c22f758 100644 --- a/src/southbridge/amd/pi/hudson/pci_devs.h +++ b/src/southbridge/amd/pi/hudson/pci_devs.h @@ -28,6 +28,11 @@ #define XHCI_DEVID 0x7814 #define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC) +#define XHCI2_DEV 0x10 +#define XHCI2_FUNC 1 +#define XHCI2_DEVID 0x7814 +#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC) + /* SATA */ #define SATA_DEV 0x11 #define SATA_FUNC 0 @@ -69,6 +74,14 @@ #define SMBUS_DEVID 0x780B #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) +/* IDE */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) +#define IDE_DEV 0x14 +#define IDE_FUNC 1 +# define IDE_DEVID 0x780C +# define IDE_DEVFN PCI_DEVFN(IDE_DEV,IDE_FUNC) +#endif + /* HD Audio */ #define HDA_DEV 0x14 #define HDA_FUNC 2 @@ -93,4 +106,21 @@ #define SD_DEVID 0x7806 #define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC) +/* PCIe Ports */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) +#define SB_PCIE_DEV 0x15 +#define SB_PCIE_PORT1_FUNC 0 +#define SB_PCIE_PORT2_FUNC 1 +#define SB_PCIE_PORT3_FUNC 2 +#define SB_PCIE_PORT4_FUNC 3 +#define SB_PCIE_PORT1_DEVID 0x7820 +#define SB_PCIE_PORT2_DEVID 0x7821 +#define SB_PCIE_PORT3_DEVID 0x7822 +#define SB_PCIE_PORT4_DEVID 0x7823 +#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC) +#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC) +#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC) +#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC) +#endif + #endif /* _PI_HUDSON_PCI_DEVS_H_ */ |