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author | Martin Roth <gaumless@gmail.com> | 2015-04-26 18:53:26 -0600 |
---|---|---|
committer | Martin Roth <gaumless@gmail.com> | 2015-04-28 21:14:56 +0200 |
commit | 595e7777e7282249b13c3d7f8a45178e76798690 (patch) | |
tree | 3f578e46e4ba70ab530e2173845423597d536bec /src/southbridge | |
parent | 562d6f30a0745b3da4c61974f8ac1b529dac9d80 (diff) | |
download | coreboot-staging-595e7777e7282249b13c3d7f8a45178e76798690.zip coreboot-staging-595e7777e7282249b13c3d7f8a45178e76798690.tar.gz |
Kconfig whitespace fixes
trivial whitespace fixes. Mostly changing leading spaces to tabs.
Change-Id: I0bdfe2059b90725e64adfc0bdde785b4e406969d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10000
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r-- | src/southbridge/amd/cimx/sb800/Kconfig | 18 | ||||
-rw-r--r-- | src/southbridge/amd/cimx/sb900/Kconfig | 24 | ||||
-rw-r--r-- | src/southbridge/amd/sb600/Kconfig | 4 | ||||
-rw-r--r-- | src/southbridge/intel/bd82x6x/Kconfig | 4 | ||||
-rw-r--r-- | src/southbridge/intel/i3100/Kconfig | 4 | ||||
-rw-r--r-- | src/southbridge/intel/i82801gx/Kconfig | 2 | ||||
-rw-r--r-- | src/southbridge/intel/i82801ix/Kconfig | 2 | ||||
-rw-r--r-- | src/southbridge/intel/ibexpeak/Kconfig | 4 | ||||
-rw-r--r-- | src/southbridge/intel/lynxpoint/Kconfig | 4 | ||||
-rw-r--r-- | src/southbridge/intel/sch/Kconfig | 4 |
10 files changed, 35 insertions, 35 deletions
diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index ac25e89..891a8e0 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -27,8 +27,8 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 if SOUTHBRIDGE_AMD_CIMX_SB800 config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/cimx/sb800/bootblock.c" + string + default "southbridge/amd/cimx/sb800/bootblock.c" config ENABLE_IDE_COMBINED_MODE bool "Enable SATA IDE combined mode" @@ -72,15 +72,15 @@ config SB800_SATA_RAID endchoice config SB800_SATA_MODE - hex + hex depends on (SB800_SATA_IDE || SB800_SATA_RAID || SB800_SATA_AHCI) default "0x0" if SB800_SATA_IDE default "0x1" if SB800_SATA_RAID default "0x2" if SB800_SATA_AHCI config SB_SUPERIO_HWM - bool - default n + bool + default n if SB800_SATA_AHCI config AHCI_ROM_ID @@ -100,8 +100,8 @@ if SB800_SATA_RAID config RAID_ROM_ID string "RAID device PCI IDs" default "1002,4393" - help - 1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode + help + 1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode config RAID_ROM_FILE string "RAID ROM path and filename" @@ -109,8 +109,8 @@ config RAID_ROM_FILE default "site-local/sb800/raid.bin" config RAID_MISC_ROM_FILE - string "RAID Misc ROM path and filename" - default "site-local/sb800/misc.bin" + string "RAID Misc ROM path and filename" + default "site-local/sb800/misc.bin" depends on SB800_SATA_RAID config RAID_MISC_ROM_POSITION diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig index 3bef95a..be94c69 100644 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ b/src/southbridge/amd/cimx/sb900/Kconfig @@ -29,30 +29,30 @@ config SATA_CONTROLLER_MODE hex default 0x0 help - 0x0 = Native IDE mode. - 0x1 = RAID mode. - 0x2 = AHCI mode. - 0x3 = Legacy IDE mode. - 0x4 = IDE->AHCI mode. - 0x5 = AHCI mode as 7804 ID (AMD driver). - 0x6 = IDE->AHCI mode as 7804 ID (AMD driver). + 0x0 = Native IDE mode. + 0x1 = RAID mode. + 0x2 = AHCI mode. + 0x3 = Legacy IDE mode. + 0x4 = IDE->AHCI mode. + 0x5 = AHCI mode as 7804 ID (AMD driver). + 0x6 = IDE->AHCI mode as 7804 ID (AMD driver). config PCIB_ENABLE bool default n help - n = Disable PCI Bridge Device 14 Function 4. - y = Enable PCI Bridge Device 14 Function 4. + n = Disable PCI Bridge Device 14 Function 4. + y = Enable PCI Bridge Device 14 Function 4. config ACPI_SCI_IRQ hex default 0x9 help - Set SCI IRQ to 9. + Set SCI IRQ to 9. config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/cimx/sb900/bootblock.c" + string + default "southbridge/amd/cimx/sb900/bootblock.c" endif #SOUTHBRIDGE_AMD_CIMX_SB900 diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig index 4d5fff4..1276bbb 100644 --- a/src/southbridge/amd/sb600/Kconfig +++ b/src/southbridge/amd/sb600/Kconfig @@ -52,7 +52,7 @@ config SATA_MODE default 0 if SATA_MODE_AHCI config HPET_MIN_TICKS - hex - default 0x14 + hex + default 0x14 endif diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 767193e..970605c 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -79,9 +79,9 @@ config BUILD_WITH_FAKE_IFD support this yet. But there is a patch pending [1]. WARNING: Never write a complete coreboot.rom to your flash ROM if it - was built with a fake IFD. It just won't work. + was built with a fake IFD. It just won't work. - [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html + [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html config IFD_BIOS_SECTION depends on BUILD_WITH_FAKE_IFD diff --git a/src/southbridge/intel/i3100/Kconfig b/src/southbridge/intel/i3100/Kconfig index 9a535d7..9dd8a38 100644 --- a/src/southbridge/intel/i3100/Kconfig +++ b/src/southbridge/intel/i3100/Kconfig @@ -7,8 +7,8 @@ config SOUTHBRIDGE_INTEL_I3100 if SOUTHBRIDGE_INTEL_I3100 config HPET_MIN_TICKS - hex - default 0x90 + hex + default 0x90 endif diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index d8c73be..f845d1d 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -34,7 +34,7 @@ config EHCI_BAR default 0xfef00000 config BOOTBLOCK_SOUTHBRIDGE_INIT - string + string default "southbridge/intel/i82801gx/bootblock.c" config HPET_MIN_TICKS diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index d8a32e5..7428d00 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -40,7 +40,7 @@ config HPET_MIN_TICKS default 0x80 config BOOTBLOCK_SOUTHBRIDGE_INIT - string + string default "southbridge/intel/i82801ix/bootblock.c" endif diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 07a5ac2..b47bf99 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -69,9 +69,9 @@ config BUILD_WITH_FAKE_IFD support this yet. But there is a patch pending [1]. WARNING: Never write a complete coreboot.rom to your flash ROM if it - was built with a fake IFD. It just won't work. + was built with a fake IFD. It just won't work. - [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html + [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html config IFD_BIOS_SECTION diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 0f52011..4797e96 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -71,9 +71,9 @@ config BUILD_WITH_FAKE_IFD support this yet. But there is a patch pending [1]. WARNING: Never write a complete coreboot.rom to your flash ROM if it - was built with a fake IFD. It just won't work. + was built with a fake IFD. It just won't work. - [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html + [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html config IFD_BIOS_SECTION depends on BUILD_WITH_FAKE_IFD diff --git a/src/southbridge/intel/sch/Kconfig b/src/southbridge/intel/sch/Kconfig index d320a53..1c0f6f0 100644 --- a/src/southbridge/intel/sch/Kconfig +++ b/src/southbridge/intel/sch/Kconfig @@ -47,8 +47,8 @@ config CMC_FILE binary. config HPET_MIN_TICKS - hex - default 0x80 + hex + default 0x80 endif |