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author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-02-10 22:21:39 -0600 |
---|---|---|
committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-16 21:02:30 +0100 |
commit | 033bb4bc8d620288ed82fe982a32f567060499b6 (patch) | |
tree | bba24a07d463455825363b54894da14a6ba07025 /src/southbridge | |
parent | 4f731f2eabc9ef2c381b71515a3b2ff203c8653e (diff) | |
download | coreboot-staging-033bb4bc8d620288ed82fe982a32f567060499b6.zip coreboot-staging-033bb4bc8d620288ed82fe982a32f567060499b6.tar.gz |
acpi: Generate valid ACPI processor objects
The existing code generated invalid ACPI processor objects
if the core number was greater than 9. The first invalid
object instance was autocorrected by Linux, but subsequent
instances conflicted with each other, leading to a failure
to boot if more than 10 CPU cores were installed.
The modified code will function with up to 99 cores.
Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8422
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r-- | src/southbridge/amd/agesa/hudson/hudson.c | 2 | ||||
-rw-r--r-- | src/southbridge/amd/cimx/sb800/fadt.c | 2 | ||||
-rw-r--r-- | src/southbridge/amd/pi/hudson/hudson.c | 2 | ||||
-rw-r--r-- | src/southbridge/amd/sb700/early_setup.c | 2 | ||||
-rw-r--r-- | src/southbridge/amd/sb800/early_setup.c | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index 4ddfea2..6d05609 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -147,7 +147,7 @@ static void hudson_init_acpi_ports(void) pm_write16(0x62, ACPI_PM1_CNT_BLK); pm_write16(0x64, ACPI_PM_TMR_BLK); pm_write16(0x68, ACPI_GPE0_BLK); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_write16(0x66, ACPI_CPU_CONTROL); if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 9442edc..2931328 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -83,7 +83,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) val = GPE0_BLK_ADDRESS; WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ val = CPU_CNT_BLK_ADDRESS; WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val); val = 0; diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index 5c55065..5db9d14 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -107,7 +107,7 @@ static void hudson_init_acpi_ports(void) pm_write16(0x62, ACPI_PM1_CNT_BLK); pm_write16(0x64, ACPI_PM_TMR_BLK); pm_write16(0x68, ACPI_GPE0_BLK); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pm_write16(0x66, ACPI_CPU_CONTROL); if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 855cbc4..94f33b7 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -56,7 +56,7 @@ static void sb700_acpi_init(void) pmio_write(0x28, ACPI_GPE0_BLK & 0xFF); pmio_write(0x29, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pmio_write(0x26, ACPI_CPU_CONTROL & 0xFF); pmio_write(0x27, ACPI_CPU_CONTROL >> 8); diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 24aa200..69bc3bd 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -53,7 +53,7 @@ static void sb800_acpi_init(void) pmio_write(0x68, ACPI_GPE0_BLK & 0xFF); pmio_write(0x69, ACPI_GPE0_BLK >> 8); - /* CpuControl is in \_PR.CPU0, 6 bytes */ + /* CpuControl is in \_PR.CP00, 6 bytes */ pmio_write(0x66, ACPI_CPU_CONTROL & 0xFF); pmio_write(0x67, ACPI_CPU_CONTROL >> 8); |