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| author | Yidi Lin <yidi.lin@mediatek.com> | 2015-11-23 15:08:44 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-12-03 14:23:01 +0100 |
| commit | 5e2cfb5cbb4dba71bb9963fa9a183beb1ed6f9d0 (patch) | |
| tree | 16667175f1037ec614c568ba9df797e163d75189 /src/soc | |
| parent | a8aef3acbc0aea2dd594f7133a7024f3babf764a (diff) | |
| download | coreboot-staging-5e2cfb5cbb4dba71bb9963fa9a183beb1ed6f9d0.zip coreboot-staging-5e2cfb5cbb4dba71bb9963fa9a183beb1ed6f9d0.tar.gz | |
mediatek/mt8173: move PRERAM_CBFS_CACHE from SRAM_L2C
L2C will be released after DRAM is initialized. Move PRERAM_CBFS_CACHE
from SRAM_L2C to ensure that it can be switched correctly.
BRANCH=none
BUG=chrome-os-partner47952
TEST=none
Change-Id: I255a0116148777d384dda43682365a5e2375cb5d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 19fcc170e57da514aee9e22289619729ddc2f792
Original-Change-Id: If3d9c1ef05dee0a10ee9151b63b8fd92cc9def51
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313888
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12602
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/mediatek/mt8173/include/soc/memlayout.ld | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/mediatek/mt8173/include/soc/memlayout.ld b/src/soc/mediatek/mt8173/include/soc/memlayout.ld index a703808..f41ce34 100644 --- a/src/soc/mediatek/mt8173/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8173/include/soc/memlayout.ld @@ -34,14 +34,14 @@ SECTIONS SRAM_L2C_START(0x000C0000) BOOTBLOCK(0x000C1000, 85K) VERSTAGE(0x000D7000, 114K) - PRERAM_CBFS_CACHE(0x000F6000, 16K) SRAM_L2C_END(0x00100000) SRAM_START(0x00100000) VBOOT2_WORK(0x00100000, 12K) PRERAM_CBMEM_CONSOLE(0x00103000, 16K) - TIMESTAMP(0x00107000, 4K) - ROMSTAGE(0x00108000, 92K) + PRERAM_CBFS_CACHE(0x00107000, 16K) + TIMESTAMP(0x0010B000, 4K) + ROMSTAGE(0x0010C000, 92K) STACK(0x00124000, 16K) TTB(0x00128000, 28K) DMA_COHERENT(0x0012F000, 4K) |
