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| author | Aaron Durbin <adurbin@chromium.org> | 2014-06-27 16:43:59 -0500 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-03-04 18:24:18 +0100 |
| commit | 1ac4e591bfcfd135ab46843fcbee0342e21a8689 (patch) | |
| tree | 69ba80e4fef8666b99368464e889a926f93d6941 /src/soc/nvidia/tegra132/Makefile.inc | |
| parent | 650d11ce94dea9ecc3fee3c2eb4dcb423af3f503 (diff) | |
| download | coreboot-staging-1ac4e591bfcfd135ab46843fcbee0342e21a8689.zip coreboot-staging-1ac4e591bfcfd135ab46843fcbee0342e21a8689.tar.gz | |
t132: Add shared romstage
There's no reason to duplicate code in the mainboards. Therefore,
drive the flow of romstage boot in the SoC. This allows for
easier scaling with multiple devices.
BUG=None
BRANCH=None
TEST=Built and booted to same place as before.
Original-Change-Id: I0d4df84034b19353daad0da1f722b820596c4f55
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205992
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie74f0eb1c983aff92d3cbafb7fe7d9d7cb65ae19
Reviewed-on: http://review.coreboot.org/8575
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/soc/nvidia/tegra132/Makefile.inc')
| -rw-r--r-- | src/soc/nvidia/tegra132/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 855ef24..a984674 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -24,6 +24,7 @@ romstage-y += spi.c romstage-y += i2c.c romstage-y += dma.c romstage-y += monotonic_timer.c +romstage-y += romstage.c romstage-y += sdram.c romstage-y += sdram_lp0.c romstage-y += ../tegra/gpio.c |
