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| author | Martin Roth <martin.roth@se-eng.com> | 2014-11-18 19:52:46 -0700 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-12-05 16:22:42 +0100 |
| commit | bdfe98f92fc1e9a69aa30ba87bb679dc28e9727c (patch) | |
| tree | 0313e18501545d9dd6b3c1ef5b931661a6575c41 /src/soc/intel/fsp_baytrail | |
| parent | 12d86e75b067313e3464ebbc9d1ab2cd62fd61fc (diff) | |
| download | coreboot-staging-bdfe98f92fc1e9a69aa30ba87bb679dc28e9727c.zip coreboot-staging-bdfe98f92fc1e9a69aa30ba87bb679dc28e9727c.tar.gz | |
fsp_baytrail: update printk to use FSP_INFO_LEVEL
Update the printk statements to use FSP_INFO_LEVEL instead of
BIOS_DEBUG. These values are currently identical, but by using the
second #define, it lets them all be changed as a unit. This can
be overridden for a particular platform by adding a #define in
chipset_fsp_util.c.
Change-Id: Idbf7e55090230ec940c7c8cd3ec8632461561428
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7520
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/soc/intel/fsp_baytrail')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index 623a7ca..6212966 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -87,7 +87,7 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U { ROMSTAGE_CONST struct device *dev; ROMSTAGE_CONST config_t *config; - printk(BIOS_DEBUG, "Configure Default UPD Data\n"); + printk(FSP_INFO_LEVEL, "Configure Default UPD Data\n"); dev = dev_find_slot(0, SOC_DEV_FUNC); config = dev->chip_info; @@ -119,13 +119,13 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U if (config->PcdMrcInitTsegSize != TSEG_SIZE_DEFAULT) UpdData->PcdMrcInitTsegSize = config->PcdMrcInitTsegSize - 1; - printk(BIOS_DEBUG, "GTT Size:\t\t%d MB\n", UpdData->PcdGttSize); - printk(BIOS_DEBUG, "Tseg Size:\t\t%d MB\n", UpdData->PcdMrcInitTsegSize); - printk(BIOS_DEBUG, "Aperture Size:\t\t%d MB\n", + printk(FSP_INFO_LEVEL, "GTT Size:\t\t%d MB\n", UpdData->PcdGttSize); + printk(FSP_INFO_LEVEL, "Tseg Size:\t\t%d MB\n", UpdData->PcdMrcInitTsegSize); + printk(FSP_INFO_LEVEL, "Aperture Size:\t\t%d MB\n", APERTURE_SIZE_BASE << UpdData->PcdApertureSize); - printk(BIOS_DEBUG, "IGD Memory Size:\t%d MB\n", + printk(FSP_INFO_LEVEL, "IGD Memory Size:\t%d MB\n", UpdData->PcdIgdDvmt50PreAlloc * IGD_MEMSIZE_MULTIPLIER); - printk(BIOS_DEBUG, "MMIO Size:\t\t%d MB\n", UpdData->PcdMrcInitMmioSize); + printk(FSP_INFO_LEVEL, "MMIO Size:\t\t%d MB\n", UpdData->PcdMrcInitMmioSize); /* Advance dev to PCI device 0.0 */ for (dev = &dev_root; dev; dev = dev_find_next_pci_device(dev)){ @@ -171,10 +171,10 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U /* Gold2 and earlier FSP: ISPEnable is the filed */ /* next to PcdGttSize in UPD_DATA_REGION struct */ *(&(UpdData->PcdGttSize)+sizeof(UINT8)) = dev->enabled; - printk (BIOS_DEBUG, + printk (FSP_INFO_LEVEL, "Baytrail Gold2 or earlier FSP, adjust ISPEnable offset.\n"); } - printk(BIOS_DEBUG, "MIPI/ISP:\t\t%s\n", + printk(FSP_INFO_LEVEL, "MIPI/ISP:\t\t%s\n", UpdData->PcdEnableSdio?"Enabled":"Disabled"); break; case EMMC_DEV_FUNC: /* EMMC 4.1*/ @@ -204,18 +204,18 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U } if (UpdData->PcdEnableLpe < sizeof(acpi_pci_mode_strings) / sizeof (char *)) - printk(BIOS_DEBUG, "Lpe:\t\t\t%s\n", + printk(FSP_INFO_LEVEL, "Lpe:\t\t\t%s\n", acpi_pci_mode_strings[UpdData->PcdEnableLpe]); if (UpdData->PcdeMMCBootMode < sizeof(emmc_mode_strings) / sizeof (char *)) - printk(BIOS_DEBUG, "eMMC Mode:\t\t%s", + printk(FSP_INFO_LEVEL, "eMMC Mode:\t\t%s", emmc_mode_strings[UpdData->PcdeMMCBootMode]); if (UpdData->PcdEnableSata) - printk(BIOS_DEBUG, "SATA Mode:\t\t%s\n", + printk(FSP_INFO_LEVEL, "SATA Mode:\t\t%s\n", UpdData->PcdSataMode?"AHCI":"IDE"); - printk(BIOS_DEBUG, "Xhci:\t\t\t%s\n", + printk(FSP_INFO_LEVEL, "Xhci:\t\t\t%s\n", UpdData->PcdEnableXhci?"Enabled":"Disabled"); /* @@ -242,7 +242,7 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U UPD_MEMDOWN_CHECK(DIMMtRTP, NO_DECREMENT_FOR_DEFAULT); UPD_MEMDOWN_CHECK(DIMMtFAW, NO_DECREMENT_FOR_DEFAULT); - printk (BIOS_DEBUG, + printk (FSP_INFO_LEVEL, "Memory Down Data Existed : %s\n"\ "- Speed (0: 800, 1: 1066, 2: 1333, 3: 1600): %d\n"\ "- Type (0: DDR3, 1: DDR3L) : %d\n"\ |
