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| author | Martin Roth <martin.roth@se-eng.com> | 2014-11-16 17:32:56 -0700 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-12-05 16:19:45 +0100 |
| commit | 09dd70ebb8f31b36d536f05af289e8edc069c893 (patch) | |
| tree | 647abf9a48259029b3e718487299e7e2c171d8e8 /src/soc/intel/fsp_baytrail | |
| parent | 3cf6aea871e4b5929959124356a7775ff21d65ac (diff) | |
| download | coreboot-staging-09dd70ebb8f31b36d536f05af289e8edc069c893.zip coreboot-staging-09dd70ebb8f31b36d536f05af289e8edc069c893.tar.gz | |
drivers/intel/fsp: add upd macros and #defines
Add macros and #defines for working with the UPD data. This makes
the code look much cleaner.
Remove the UPD_ENABLE / UPD_DISABLE from fsp_rangeley/chip.h and include
the fsp_values header instead. This fixes a conflict.
Change-Id: I72c9556065e5c7461432a4593b75da2c8a220a12
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7487
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/soc/intel/fsp_baytrail')
0 files changed, 0 insertions, 0 deletions
