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| author | Duncan Laurie <dlaurie@chromium.org> | 2014-10-01 13:47:20 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-02 17:28:15 +0200 |
| commit | d9f95070650675599e0c1dee67f0b0074eced678 (patch) | |
| tree | 611c5bf95691496a8556ff33d2923367e5b15079 /src/soc/intel/broadwell/chip.h | |
| parent | 767d245ebf2d6d797bf759d23778553ed6f2a0b2 (diff) | |
| download | coreboot-staging-d9f95070650675599e0c1dee67f0b0074eced678.zip coreboot-staging-d9f95070650675599e0c1dee67f0b0074eced678.tar.gz | |
broadwell: Disable ADSP power gating feature by default
Disable ADSP D3 and SRAM power gating features by default, and make
the devicetree.cb flags into enable flags instead of disable.
BUG=chrome-os-partner:31588
BRANCH=samus,auron
TEST=build and boot on samus
Change-Id: Ibda298b995b07a2826a406e74e0d244b1fd97746
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: b81ef37c036d61dc56e650796227dcc84a7ccc89
Original-Change-Id: Ib881290acc07819b55d776d4696bf0062df4d50e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220863
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9218
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/chip.h')
| -rw-r--r-- | src/soc/intel/broadwell/chip.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 005ab36..703c865 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -84,8 +84,9 @@ struct soc_intel_broadwell_config { uint8_t sio_i2c0_voltage; uint8_t sio_i2c1_voltage; - /* Disable ADSP power gating in D3 */ - uint8_t adsp_d3_pg_disable; + /* Enable ADSP power gating features */ + uint8_t adsp_d3_pg_enable; + uint8_t adsp_sram_pg_enable; /* * Clock Disable Map: |
