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| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-09-07 01:54:23 -0700 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-09-07 17:40:32 +0000 |
| commit | 2c482a969a546a70c2787d4d96d1ac212da11eff (patch) | |
| tree | 2e255af6918f41ae63e185726ae7620a598fcc49 /src/northbridge/intel | |
| parent | 4460703f59c58626c762a8a1244842b7a3efe0db (diff) | |
| download | coreboot-staging-2c482a969a546a70c2787d4d96d1ac212da11eff.zip coreboot-staging-2c482a969a546a70c2787d4d96d1ac212da11eff.tar.gz | |
intel: Do not hardcode the position of mrc.cache
The reason for hardcoding the position of the MRC cache was to satisfy
the alignment to the erase size of the flash chip. Hardcoding is no
longer needed, as we can specify alignment directly. In the long term,
the MRC cache will have to move to FMAP, but for now, we reduce
fragmentation in CBFS.
Note that soc/intel/common hardcoding of mrc.cache is not removed, as
the mrc cache implementation there does not use CBFS to find the cache
region, and needs a hardcoded address.
Change-Id: I5b9fc1ba58bb484c7b5f687368172d9ebe625bfd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11527
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/haswell/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/Makefile.inc | 6 |
3 files changed, 3 insertions, 7 deletions
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index ad4b2ba..8d038da 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -50,7 +50,7 @@ $(obj)/mrc.cache: $(obj)/config.h cbfs-files-y += mrc.cache mrc.cache-file := $(obj)/mrc.cache -mrc.cache-position := 0xfffe0000 +mrc.cache-align := 0x10000 mrc.cache-type := mrc_cache endif diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index e5b4385..63c49f2 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -42,7 +42,7 @@ $(obj)/mrc.cache: cbfs-files-y += mrc.cache mrc.cache-file := $(obj)/mrc.cache -mrc.cache-position := 0xfffe0000 +mrc.cache-align := 0x10000 mrc.cache-type := mrc_cache endif diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 407b61d..52fe23c 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -59,11 +59,7 @@ $(obj)/mrc.cache: $(obj)/config.h cbfs-files-y += mrc.cache mrc.cache-file := $(obj)/mrc.cache -mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) := 0xfffd0000 -mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) := 0xfffd0000 -mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) := 0xfffe0000 -mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) := 0xfffe0000 -mrc.cache-position := $(mrc-cache-position-y) +mrc.cache-align := 0x10000 mrc.cache-type := mrc_cache endif |
