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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-12-18 13:22:37 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-12-18 13:22:37 +0000 |
| commit | 405721d45c8f7cd58c2466e43df8c2aee6f8e714 (patch) | |
| tree | d9c981c99cf28f931032dabb26094494622f7bb6 /src/northbridge/intel/sch/port_access.c | |
| parent | a0360af0f1645d91b139022353f7a3a9f7f85f8a (diff) | |
| download | coreboot-staging-405721d45c8f7cd58c2466e43df8c2aee6f8e714.zip coreboot-staging-405721d45c8f7cd58c2466e43df8c2aee6f8e714.tar.gz | |
Fix a few whitespace and coding style issues.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/sch/port_access.c')
| -rw-r--r-- | src/northbridge/intel/sch/port_access.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/src/northbridge/intel/sch/port_access.c b/src/northbridge/intel/sch/port_access.c index 73e03c8..bdd6b17 100644 --- a/src/northbridge/intel/sch/port_access.c +++ b/src/northbridge/intel/sch/port_access.c @@ -5,8 +5,7 @@ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. + * published by the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -44,32 +43,33 @@ * | Data | * | | * ---------------------------------------------------------------------------- - * */ + #define MSG_OPCODE_READ 0xD0000000 #define MSG_OPCODE_WRITE 0xE0000000 #define MCR 0xD0 #define MDR 0xD4 -int sch_port_access_read(int port,int reg, int bytes) +int sch_port_access_read(int port, int reg, int bytes) { - pci_write_config32(PCI_DEV(0, 0, 0), MCR, (MSG_OPCODE_READ |(port <<16) | (reg << 8) )); + pci_write_config32(PCI_DEV(0, 0, 0), MCR, + (MSG_OPCODE_READ | (port << 16) | (reg << 8))); return pci_read_config32(PCI_DEV(0, 0, 0), MDR); } -void sch_port_access_write(int port,int reg,int bytes,long data) +void sch_port_access_write(int port, int reg, int bytes, long data) { - pci_write_config32(PCI_DEV(0, 0, 0), MDR,data); - pci_write_config32(PCI_DEV(0, 0, 0), MCR, (MSG_OPCODE_WRITE |(port <<16) | (reg << 8) )); + pci_write_config32(PCI_DEV(0, 0, 0), MDR, data); + pci_write_config32(PCI_DEV(0, 0, 0), MCR, + (MSG_OPCODE_WRITE | (port << 16) | (reg << 8))); pci_read_config32(PCI_DEV(0, 0, 0), MDR); } -void sch_port_access_write_ram_cmd(int cmd,int port,int reg,int data) +void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data) { - - pci_write_config32(PCI_DEV(0, 0, 0), MDR,data); - pci_write_config32(PCI_DEV(0, 0, 0), MCR, ((cmd << 24) |(port <<16) | (reg << 8))); + pci_write_config32(PCI_DEV(0, 0, 0), MDR, data); + pci_write_config32(PCI_DEV(0, 0, 0), MCR, + ((cmd << 24) | (port << 16) | (reg << 8))); pci_read_config32(PCI_DEV(0, 0, 0), MDR); } - |
