northbridge/intel/pineview: Add minimal Pineview northbridge

Based on i945.  Tested on Intel D510MO mainboard,
board boots to UART console with this code.

Change-Id: I1d92a1aa6d6d767bda8379807dc26b50b9de75c9
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/10073
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

7 files changed, 339 insertions, 0 deletions

diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
new file mode 100644
index 0000000..6253b84
--- /dev/null
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -0,0 +1,39 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+## Copyright (C) 2015  Damien Zammit <damien@zamaudio.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+config NORTHBRIDGE_INTEL_PINEVIEW
+	bool
+
+if NORTHBRIDGE_INTEL_PINEVIEW
+
+config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select MMCONF_SUPPORT
+	select MMCONF_SUPPORT_DEFAULT
+	select HAVE_DEBUG_RAM_SETUP
+	select LAPIC_MONOTONIC_TIMER
+	select VGA
+	select PER_DEVICE_ACPI_TABLES
+
+config BOOTBLOCK_NORTHBRIDGE_INIT
+	string
+	default "northbridge/intel/pineview/bootblock.c"
+
+config VGA_BIOS_ID
+	string
+	default "8086,a001"
+
+endif
diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc
new file mode 100644
index 0000000..9330b17
--- /dev/null
+++ b/src/northbridge/intel/pineview/Makefile.inc
@@ -0,0 +1,24 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2009 coresystems GmbH
+# Copyright (C) 2015  Damien Zammit <damien@zamaudio.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+ifeq ($(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW),y)
+
+ramstage-y += ram_calc.c
+ramstage-y += acpi.c
+
+romstage-y += ram_calc.c
+
+endif
diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c
new file mode 100644
index 0000000..f29d235
--- /dev/null
+++ b/src/northbridge/intel/pineview/acpi.c
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015  Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpigen.h>
+#include <arch/acpi.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <northbridge/intel/pineview/pineview.h>
+#include <types.h>
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	device_t dev;
+	u32 pciexbar = 0;
+	u32 pciexbar_reg;
+	u32 reg32;
+	int max_buses;
+	const struct {
+		u16 num_buses;
+		u32 addr_mask;
+	} busmask[] = {
+		{256, 0xff000000},
+		{128, 0xf8000000},
+		{64,  0xfc000000},
+		{0,   0},
+	};
+
+	dev = dev_find_slot(0, PCI_DEVFN(0,0));
+	if (!dev)
+		return current;
+
+	pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
+
+	// MMCFG not supported or not enabled.
+	if (!(pciexbar_reg & (1 << 0))) {
+		printk(BIOS_WARNING, "WARNING: MMCONF not set\n");
+		return current;
+	}
+
+	reg32 = (pciexbar_reg >> 1) & 3;
+	pciexbar = pciexbar_reg & busmask[reg32].addr_mask;
+	max_buses = busmask[reg32].num_buses;
+
+	if (!pciexbar) {
+		printk(BIOS_WARNING, "WARNING: pciexbar invalid\n");
+		return current;
+	}
+
+	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
+			pciexbar, 0x0, 0x0, max_buses - 1);
+
+	return current;
+}
diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c
new file mode 100644
index 0000000..1c04c28
--- /dev/null
+++ b/src/northbridge/intel/pineview/bootblock.c
@@ -0,0 +1,8 @@
+#include <arch/io.h>
+#define PCIEXBAR 0x60
+
+static void bootblock_northbridge_init(void)
+{
+	pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR,
+		CONFIG_MMCONF_BASE_ADDRESS | 4 | 1);
+}
diff --git a/src/northbridge/intel/pineview/iomap.h b/src/northbridge/intel/pineview/iomap.h
new file mode 100644
index 0000000..6cced82
--- /dev/null
+++ b/src/northbridge/intel/pineview/iomap.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015  Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef PINEVIEW_IOMAP_H
+#define PINEVIEW_IOMAP_H
+
+/* 4 KB per PCIe device */
+#define DEFAULT_PCIEXBAR	CONFIG_MMCONF_BASE_ADDRESS
+
+#define DEFAULT_MCHBAR		0xfed14000	/* 16 KB */
+#define DEFAULT_DMIBAR		0xfed18000	/* 4 KB */
+#define DEFAULT_EPBAR		0xfed19000	/* 4 KB */
+
+#endif /* PINEVIEW_IOMAP_H */
diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h
new file mode 100644
index 0000000..4b3b0b1
--- /dev/null
+++ b/src/northbridge/intel/pineview/pineview.h
@@ -0,0 +1,116 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015  Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef NORTHBRIDGE_INTEL_PINEVIEW_H
+#define NORTHBRIDGE_INTEL_PINEVIEW_H
+
+#include <northbridge/intel/pineview/iomap.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+
+/* Device 0:0.0 PCI configuration space (Host Bridge) */
+
+#define EPBAR		0x40
+#define MCHBAR		0x48
+#define PCIEXBAR	0x60
+#define DMIBAR		0x68
+#define PMIOBAR		0x78
+
+#define GGC		0x52			/* GMCH Graphics Control */
+
+#define DEVEN		0x54			/* Device Enable */
+#define  DEVEN_D0F0 (1 << 0)
+#define  DEVEN_D1F0 (1 << 1)
+#define  DEVEN_D2F0 (1 << 3)
+#define  DEVEN_D2F1 (1 << 4)
+
+#ifndef BOARD_DEVEN
+#define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 )
+#endif /* BOARD_DEVEN */
+
+#define PAM0		0x90
+#define PAM1		0x91
+#define PAM2		0x92
+#define PAM3		0x93
+#define PAM4		0x94
+#define PAM5		0x95
+#define PAM6		0x96
+
+#define LAC		0x97	/* Legacy Access Control */
+#define REMAPBASE	0x98
+#define REMAPLIMIT	0x9a
+#define SMRAM		0x9d	/* System Management RAM Control */
+#define ESMRAM		0x9e	/* Extended System Management RAM Control */
+
+#define TOM		0xa0
+#define TOUUD		0xa2
+#define GBSM		0xa4
+#define BGSM		0xa8
+#define TSEGMB		0xac
+#define TOLUD		0xb0	/* Top of Low Used Memory */
+#define ERRSTS		0xc8
+#define ERRCMD		0xca
+#define SMICMD		0xcc
+#define SCICMD		0xce
+#define CGDIS		0xd8
+#define SKPAD		0xdc	/* Scratchpad Data */
+#define CAPID0		0xe0
+#define DEV0T		0xf0
+#define MSLCK		0xf4
+#define MID0		0xf8
+#define DEBUP0		0xfc
+
+/* Device 0:1.0 PCI configuration space (PCI Express) */
+
+#define BCTRL1		0x3e	/* 16bit */
+#define PEGSTS		0x214	/* 32bit */
+
+
+/* Device 0:2.0 PCI configuration space (Graphics Device) */
+
+#define GMADR		0x18
+#define GTTADR		0x1c
+#define BSM		0x5c
+#define GCFC		0xf0	/* Graphics Clock Frequency & Gating Control */
+
+
+/*
+ * MCHBAR
+ */
+
+#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x))
+#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x))
+#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x))
+
+/*
+ * EPBAR - Egress Port Root Complex Register Block
+ */
+
+#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
+#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))
+#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))
+
+/*
+ * DMIBAR
+ */
+
+#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
+#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
+#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
+
+/* provided by mainboard code */
+void setup_ich7_gpios(void);
+
+#endif /* NORTHBRIDGE_INTEL_PINEVIEW_H */
diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c
new file mode 100644
index 0000000..e9f8eed
--- /dev/null
+++ b/src/northbridge/intel/pineview/ram_calc.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015  Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Use simple device model for this file even in ramstage */
+#define __SIMPLE_DEVICE__
+
+#include <arch/io.h>
+#include <cbmem.h>
+#include <northbridge/intel/pineview/pineview.h>
+
+static void *find_ramtop(void)
+{
+	uint32_t tom;
+
+	if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) {
+		/* IGD enabled, get top of Memory from BSM register */
+		tom = pci_read_config32(PCI_DEV(0,2,0), BSM);
+	} else
+		tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24;
+
+	/* if TSEG enabled subtract size */
+	switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM) & 0x07) {
+	case 0x01:
+		/* 1MB TSEG */
+		tom -= 0x100000;
+		break;
+	case 0x03:
+		/* 2MB TSEG */
+		tom -= 0x200000;
+		break;
+	case 0x05:
+		/* 8MB TSEG */
+		tom -= 0x800000;
+		break;
+	default:
+		/* TSEG either disabled or invalid */
+		break;
+	}
+	return (void *)tom;
+}
+
+void *cbmem_top(void)
+{
+	return find_ramtop();
+}