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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2013-11-12 22:32:08 +0100 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2013-11-25 20:23:38 +0100 |
| commit | c6f6be0929ccef4c551f9640300972e7bc8600ec (patch) | |
| tree | 642cdabcd43f4d86101868a56d87abed5317d780 /src/northbridge/intel/nehalem/bootblock.c | |
| parent | 888d559b0373cb956314b8087439378c14a16918 (diff) | |
| download | coreboot-staging-c6f6be0929ccef4c551f9640300972e7bc8600ec.zip coreboot-staging-c6f6be0929ccef4c551f9640300972e7bc8600ec.tar.gz | |
Support for nehalem northbridge
Including raminit
Change-Id: If1dd3855181481b8b928adf0fdb40b29d15897db
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4044
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/intel/nehalem/bootblock.c')
| -rw-r--r-- | src/northbridge/intel/nehalem/bootblock.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/northbridge/intel/nehalem/bootblock.c b/src/northbridge/intel/nehalem/bootblock.c new file mode 100644 index 0000000..8382205 --- /dev/null +++ b/src/northbridge/intel/nehalem/bootblock.c @@ -0,0 +1,7 @@ +#include <arch/io.h> + +static void bootblock_northbridge_init(void) +{ + pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, DEFAULT_PCIEXBAR | 1); + pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x54, 0); +} |
