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author | Vladimir Serbinenko <phcoder@gmail.com> | 2013-11-12 22:32:08 +0100 |
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committer | Vladimir Serbinenko <phcoder@gmail.com> | 2013-11-25 20:23:38 +0100 |
commit | c6f6be0929ccef4c551f9640300972e7bc8600ec (patch) | |
tree | 642cdabcd43f4d86101868a56d87abed5317d780 /src/northbridge/intel/nehalem/Makefile.inc | |
parent | 888d559b0373cb956314b8087439378c14a16918 (diff) | |
download | coreboot-staging-c6f6be0929ccef4c551f9640300972e7bc8600ec.zip coreboot-staging-c6f6be0929ccef4c551f9640300972e7bc8600ec.tar.gz |
Support for nehalem northbridge
Including raminit
Change-Id: If1dd3855181481b8b928adf0fdb40b29d15897db
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4044
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/intel/nehalem/Makefile.inc')
-rw-r--r-- | src/northbridge/intel/nehalem/Makefile.inc | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc new file mode 100644 index 0000000..6c53f49 --- /dev/null +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -0,0 +1,43 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2010 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-y += northbridge.c +ramstage-y += gma.c + +ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-y += ../sandybridge/mrccache.c + +romstage-y += raminit.c +romstage-y += early_init.c +romstage-y += ../sandybridge/mrccache.c +romstage-y += ../../../arch/x86/lib/walkcbfs.S + +smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c + +$(obj)/mrc.cache: + dd if=/dev/zero count=1 \ + bs=$(shell printf "%d" $(CONFIG_TRAINING_CACHE_SIZE) ) | \ + tr '\000' '\377' > $@ + +cbfs-files-y += mrc.cache +mrc.cache-file := $(obj)/mrc.cache +mrc.cache-position := 0xfff80000 +mrc.cache-type := 0xac + +$(obj)/northbridge/intel/nehalem/acpi.ramstage.o : $(obj)/build.h |