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author | Stefan Reinauer <stepan@coresystems.de> | 2008-10-29 04:51:07 +0000 |
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committer | Stefan Reinauer <stepan@openbios.org> | 2008-10-29 04:51:07 +0000 |
commit | 278534d00734a1f4c3f252f11ca234a6517a590b (patch) | |
tree | 8847383901be6363843888dca10c597664624e5b /src/northbridge/intel/i945/udelay.c | |
parent | 00a889c8aabd7b731622d5ff0e765f69e158de2b (diff) | |
download | coreboot-staging-278534d00734a1f4c3f252f11ca234a6517a590b.zip coreboot-staging-278534d00734a1f4c3f252f11ca234a6517a590b.tar.gz |
Support for the Intel 945 northbridge.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i945/udelay.c')
-rw-r--r-- | src/northbridge/intel/i945/udelay.c | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c new file mode 100644 index 0000000..9740c08 --- /dev/null +++ b/src/northbridge/intel/i945/udelay.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cpu/x86/tsc.h> +#include <cpu/x86/msr.h> + +/** + * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock + */ + +static void udelay(u32 us) +{ + u32 dword; + tsc_t tsc, tsc1, tscd; + msr_t msr; + u32 fsb = 0, divisor; + u32 d; + u32 dn = 0x1000000 / 2; + + msr = rdmsr(0xcd); + switch (msr.lo & 0x07) { + case 5: + fsb = 400; + break; + case 1: + fsb = 533; + break; + case 3: + fsb = 667; + break; + } + + msr = rdmsr(0x198); + divisor = (msr.hi >> 8) & 0x1f; + + d = fsb * divisor; + + tscd.hi = us / dn; + tscd.lo = (us - tscd.hi * dn) * d; + + tsc1 = rdtsc(); + dword = tsc1.lo + tscd.lo; + if ((dword < tsc1.lo) || (dword < tscd.lo)) { + tsc1.hi++; + } + tsc1.lo = dword; + tsc1.hi += tscd.hi; + + do { + tsc = rdtsc(); + } while ((tsc.hi > tsc1.hi) + || ((tsc.hi == tsc1.hi) && (tsc.lo > tsc1.lo))); + +} |