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| author | Ronald G. Minnich <rminnich@gmail.com> | 2004-08-26 16:13:40 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2004-08-26 16:13:40 +0000 |
| commit | 6707a45eb14bf28abd2a38e1b95d30d27262f347 (patch) | |
| tree | f6add8095bc5deec447bb667efe170320e69d5fc /src/northbridge/intel/i855pm/reset_test.c | |
| parent | 1ddc8eaddb54b05a9ecb5ffbf9ba3e3264f63ec3 (diff) | |
| download | coreboot-staging-6707a45eb14bf28abd2a38e1b95d30d27262f347.zip coreboot-staging-6707a45eb14bf28abd2a38e1b95d30d27262f347.tar.gz | |
just a few changes before we hit the big fun.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1641 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i855pm/reset_test.c')
| -rw-r--r-- | src/northbridge/intel/i855pm/reset_test.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/northbridge/intel/i855pm/reset_test.c b/src/northbridge/intel/i855pm/reset_test.c index 29f2d45..7c933c5 100644 --- a/src/northbridge/intel/i855pm/reset_test.c +++ b/src/northbridge/intel/i855pm/reset_test.c @@ -1,4 +1,5 @@ /* Convert to C by yhlu */ +/* converted to 855 by RGM */ #define MCH_DRC 0x70 #define DRC_DONE (1 << 29) /* If I have already booted once skip a bunch of initialization */ |
