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authorRonald G. Minnich <rminnich@gmail.com>2004-09-28 20:09:06 +0000
committerRonald G. Minnich <rminnich@gmail.com>2004-09-28 20:09:06 +0000
commita26c8ef2a0bf380d030fa88aa6e0a081c74711f3 (patch)
tree3d9d77b2efa5447e31a52ad8fc05e03f55d20ef1 /src/northbridge/intel/i855pm/raminit.c
parentc3c27a50d974e183927fc0b31b6c96800e27f5d2 (diff)
downloadcoreboot-staging-a26c8ef2a0bf380d030fa88aa6e0a081c74711f3.zip
coreboot-staging-a26c8ef2a0bf380d030fa88aa6e0a081c74711f3.tar.gz
add support for ICH4. more i955pm stuff.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1649 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i855pm/raminit.c')
-rw-r--r--src/northbridge/intel/i855pm/raminit.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/northbridge/intel/i855pm/raminit.c b/src/northbridge/intel/i855pm/raminit.c
index 8d02992..cd103d5 100644
--- a/src/northbridge/intel/i855pm/raminit.c
+++ b/src/northbridge/intel/i855pm/raminit.c
@@ -5,7 +5,7 @@
/* converted to C 6/2004 yhlu */
#define DEBUG_RAM_CONFIG 1
-
+#define ASM_CONSOLE_LOGLEVEL 10
#define dumpnorth() dump_pci_device(PCI_DEV(0, 0, 0))
/* DDR DIMM Mode register Definitions */
@@ -1512,7 +1512,7 @@ static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
dimm_mask |= (1 << i);
}
}
-#if 1
+#if 0
device = ctrl->channel1[i];
if (device) {
byte = spd_read_byte(ctrl->channel1[i], 2);
@@ -1798,12 +1798,13 @@ static void dram_finish(const struct mem_controller *ctrl)
#endif
/* Clear the ECC error bits */
+#if 0
pci_write_config8(ctrl->d0f1, 0x80, 0x03); /* dev 0, function 1, offset 80 */
pci_write_config8(ctrl->d0f1, 0x82, 0x03); /* dev 0, function 1, offset 82 */
pci_write_config32(ctrl->d0f1, 0x40, 1<<18); /* clear dev 0, function 1, offset 40; bit 18 by writing a 1 to it */
pci_write_config32(ctrl->d0f1, 0x44, 1<<18); /* clear dev 0, function 1, offset 44; bit 18 by writing a 1 to it */
-
+#endif
pci_write_config8(ctrl->d0, 0x52, 0x0d);
}
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