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author | Sven Schnelle <svens@stackframe.org> | 2012-07-12 20:05:22 +0200 |
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committer | Sven Schnelle <svens@stackframe.org> | 2012-07-16 08:40:48 +0200 |
commit | d4220691c58934420ad196d4a0903dc88388ae85 (patch) | |
tree | 694583a0da0c2730d15295ca252a8564b6d57978 /src/northbridge/intel/i5000/raminit.c | |
parent | f8878845f9cb9d30663a8bb3a3edeb1413a42388 (diff) | |
download | coreboot-staging-d4220691c58934420ad196d4a0903dc88388ae85.zip coreboot-staging-d4220691c58934420ad196d4a0903dc88388ae85.tar.gz |
i5000: Fix resource allocation
The current code didn't reserve static resource the right way.
Also reduce TOLM to 0xd0000000, because those boards have so many PCI
devices that 0xe0000000 isn't sufficient.
Change-Id: Ia75a81905eea1a096aed464b63ac154e044bc99c
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1220
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/intel/i5000/raminit.c')
-rw-r--r-- | src/northbridge/intel/i5000/raminit.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c index 841e809..ffc579a 100644 --- a/src/northbridge/intel/i5000/raminit.c +++ b/src/northbridge/intel/i5000/raminit.c @@ -1349,8 +1349,8 @@ static int i5000_dram_timing_init(struct i5000_fbd_setup *setup) i5000_setup_interleave(setup); - if ((tolm = MIN(setup->totalmem, 0xe00)) > 0xe00) - tolm = 0xe00; + if ((tolm = MIN(setup->totalmem, 0xd00)) > 0xd00) + tolm = 0xd00; tolm <<= 4; printk(BIOS_DEBUG, "TOLM: 0x%04x\n", tolm); @@ -1759,7 +1759,7 @@ void i5000_fbdimm_init(void) #if CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK if (ram_check_nodie(0x000000, 0x0a0000) || - ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xe0000000))) { + ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xd0000000))) { i5000_try_restart("RAM verification failed"); } |