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| author | Sven Schnelle <svens@stackframe.org> | 2012-02-09 21:05:20 +0100 |
|---|---|---|
| committer | Sven Schnelle <svens@stackframe.org> | 2012-02-10 10:28:18 +0100 |
| commit | 332a7e91c71697b9eb07a7974c1c248bf97e30cd (patch) | |
| tree | d2e91af8902fefa5eea4badd1652ca95da77b9ec /src/northbridge/intel/i5000/halt_second_bsp.S | |
| parent | 6d64adeaa680ea9fde3140e1d3a47d9b9270d3f8 (diff) | |
| download | coreboot-staging-332a7e91c71697b9eb07a7974c1c248bf97e30cd.zip coreboot-staging-332a7e91c71697b9eb07a7974c1c248bf97e30cd.tar.gz | |
i5000: halt second BSP
If both FSBs on i5000 are equipped with CPU packages, one CPU
from each package is elected as BSP. To prevent races between
both BSPs, hlt the second BSP.
Change-Id: I6bfcb17d34e9f028280acff1694309e37307ec21
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/615
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/intel/i5000/halt_second_bsp.S')
| -rw-r--r-- | src/northbridge/intel/i5000/halt_second_bsp.S | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S b/src/northbridge/intel/i5000/halt_second_bsp.S new file mode 100644 index 0000000..a1a1b15 --- /dev/null +++ b/src/northbridge/intel/i5000/halt_second_bsp.S @@ -0,0 +1,29 @@ + /* Save BIST result */ + + movl %eax, %ebp + + /* Read the semaphore register of i5000 (BOFL0). + If it returns zero, it means there was already + another read by another CPU */ + + movl $0x800080c0, %eax + movw $0xcf8, %dx + outl %eax, %dx + + addw $4, %dx + inl %dx, %eax + cmp $0, %eax + jne 1f + + /* degrade BSP to AP */ + mov $0x1b, %ecx + rdmsr + andl $(~0x100), %eax + wrmsr + + cli +loop: hlt + jmp loop + +1: /* Restore BIST */ + mov %ebp, %eax |
