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author | Myles Watson <mylesgw@gmail.com> | 2009-07-02 18:56:24 +0000 |
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committer | Myles Watson <mylesgw@gmail.com> | 2009-07-02 18:56:24 +0000 |
commit | 29cc9eda2021a87396ef31a6fc81daff6fd1be7a (patch) | |
tree | d3dfa07ca85547c77c5d07825fc8afcc19489076 /src/northbridge/intel/i440bx/northbridge.c | |
parent | 2468331952bae0abdc4d76dbe6cf26f05b7825e5 (diff) | |
download | coreboot-staging-29cc9eda2021a87396ef31a6fc81daff6fd1be7a.zip coreboot-staging-29cc9eda2021a87396ef31a6fc81daff6fd1be7a.tar.gz |
Move the v3 resource allocator to v2.
Major changes:
1. Separate resource allocation into:
A. Read Resources
B. Avoid fixed resources (constrain limits)
C. Allocate resources
D. Set resources
Usage notes:
Resources which have IORESOURCE_FIXED set in the flags constrain the placement
of other resources. All fixed resources will end up outside (above or below)
the allocated resources.
Domains usually start with base = 0 and limit = 2^address_bits - 1.
I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is
still there for resources. Some platforms may want to change that, but I didn't
want to break anyone's board.
Resources are allocated in a single block for memory and another for I/O.
Currently the resource allocator doesn't support holes.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i440bx/northbridge.c')
-rw-r--r-- | src/northbridge/intel/i440bx/northbridge.c | 28 |
1 files changed, 2 insertions, 26 deletions
diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 34c868e..05c614c 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -33,24 +33,6 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x7190, }; - -#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) - -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0)); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { @@ -95,7 +77,7 @@ static uint32_t find_pci_tolm(struct bus *bus) extern uint64_t high_tables_base, high_tables_size; #endif -static void pci_domain_set_resources(device_t dev) +static void i440bx_domain_set_resources(device_t dev) { device_t mc_dev; uint32_t pci_tolm; @@ -140,15 +122,9 @@ static void pci_domain_set_resources(device_t dev) assign_resources(&dev->link[0]); } -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, + .set_resources = i440bx_domain_set_resources, .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = pci_domain_scan_bus, |