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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-10-13 04:15:40 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-10-15 13:18:22 +0200 |
| commit | 697927cc35c80ddbe91d868ba1e41fb68dda815d (patch) | |
| tree | 3fafbb7f0cc4c42bbbddf073e985d5dc8891d0dd /src/northbridge/intel/haswell/raminit.c | |
| parent | 2644793ef486881f3af36bec69d5f9abf82123ac (diff) | |
| download | coreboot-staging-697927cc35c80ddbe91d868ba1e41fb68dda815d.zip coreboot-staging-697927cc35c80ddbe91d868ba1e41fb68dda815d.tar.gz | |
CBMEM: Define cbmem_top() just once for x86
It is expected this will always be a casted get_top_of_ram() call
on x86, no reason to do that under chipset.
Change-Id: I3a49abe13ca44bf4ca1e26d1b3baf954bc5a29b7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3972
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/northbridge/intel/haswell/raminit.c')
| -rw-r--r-- | src/northbridge/intel/haswell/raminit.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index c1095a7..a90b360 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -202,12 +202,6 @@ void sdram_initialize(struct pei_data *pei_data) report_memory_config(); } -void *cbmem_top(void) -{ - /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ - return (void *)get_top_of_ram(); -} - unsigned long get_top_of_ram(void) { /* |
