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| author | Noe Rubinstein <nrubinstein@proformatique.com> | 2011-05-05 15:44:40 +0200 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2011-09-09 11:40:48 +0200 |
| commit | 03169d3e1c03e76670ff7a07de7ee4fc6f601d3a (patch) | |
| tree | aa448fc0896cfe37ede9f9eaf128e4acc2480570 /src/northbridge/intel/e7525 | |
| parent | ac624a638d25645f9a9a25ee2e16224aaf921b98 (diff) | |
| download | coreboot-staging-03169d3e1c03e76670ff7a07de7ee4fc6f601d3a.zip coreboot-staging-03169d3e1c03e76670ff7a07de7ee4fc6f601d3a.tar.gz | |
Replace while with do; while to avoid repetition
Cosmetic only; replaces some 'while' loops with 'do; while' loops to
avoid repetition.
Replacement performed by the Ruby expression:
t.gsub!(/^(\s*)([^\n\{]+)\n\1(while[^\n\{;]+)\n\s*\2/,
"\\1do \\2\n\\1\\3;")
Change-Id: Ie0a4fa622df881edeaab08f59bb888a903b864fd
Signed-off-by: Noe Rubinstein <nrubinstein@proformatique.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/183
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/e7525')
| -rw-r--r-- | src/northbridge/intel/e7525/raminit.c | 55 |
1 files changed, 22 insertions, 33 deletions
diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c index 495a142..e341596 100644 --- a/src/northbridge/intel/e7525/raminit.c +++ b/src/northbridge/intel/e7525/raminit.c @@ -1104,9 +1104,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) write32(BAR+0x100, (0x83000000 | (i<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } @@ -1115,9 +1114,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR + DCALCSR, (0x83000000 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Precharg all banks */ @@ -1128,9 +1126,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* DDR1 */ write32(BAR+DCALADDR, 0x00000000); write32(BAR+DCALCSR, (0x83000002 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* EMRS dll's enabled */ @@ -1142,9 +1139,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* DDR1 */ write32(BAR+DCALADDR, 0x00000001); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* MRS reset dll's */ do_delay(); @@ -1163,9 +1159,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, mode_reg); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Precharg all banks */ @@ -1178,25 +1173,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* DDR1 */ write32(BAR+DCALADDR, 0x00000000); write32(BAR+DCALCSR, (0x83000002 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Do 2 refreshes */ do_delay(); for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); /* for good luck do 6 more */ @@ -1229,9 +1221,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, (mode_reg & ~(1<<24))); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Do only if DDR2 EMRS dll's enabled */ @@ -1240,9 +1231,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, (0x0b940001)); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } } @@ -1283,9 +1273,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x830831d8 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Bring memory subsystem on line */ |
