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| author | Yinghai Lu <yinghailu@gmail.com> | 2004-07-01 03:55:03 +0000 |
|---|---|---|
| committer | Yinghai Lu <yinghailu@gmail.com> | 2004-07-01 03:55:03 +0000 |
| commit | 70093f7875371abe52c4417c6cc3a427d20781c5 (patch) | |
| tree | f5812172eab817e66840583c669f16d4b1121531 /src/northbridge/intel/e7501/reset_test.c | |
| parent | 7dea9552d5fa10c5542e744fe1d8e0a81689e3c1 (diff) | |
| download | coreboot-staging-70093f7875371abe52c4417c6cc3a427d20781c5.zip coreboot-staging-70093f7875371abe52c4417c6cc3a427d20781c5.tar.gz | |
Intel E7501 P64H2 ICH5R support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/e7501/reset_test.c')
| -rw-r--r-- | src/northbridge/intel/e7501/reset_test.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/northbridge/intel/e7501/reset_test.c b/src/northbridge/intel/e7501/reset_test.c new file mode 100644 index 0000000..79a5cda --- /dev/null +++ b/src/northbridge/intel/e7501/reset_test.c @@ -0,0 +1,18 @@ +/* Convert to C by yhlu */ +#define MCH_DRC 0x7c +#define DRC_DONE (1 << 29) + /* If I have already booted once skip a bunch of initialization */ + /* To see if I have already booted I check to see if memory + * has been enabled. + */ +static int bios_reset_detected(void) { + uint32_t dword; + + dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC); + + if( (dword & DRC_DONE) != 0 ) { + return 1; + } + + return 0; +} |
