summaryrefslogtreecommitdiffstats
path: root/src/northbridge/amd
diff options
context:
space:
mode:
authorStefan Reinauer <stefan.reinauer@coreboot.org>2013-02-27 23:45:20 +0100
committerRonald G. Minnich <rminnich@gmail.com>2013-02-28 00:00:30 +0100
commitfd611f9c2c8c751069c6cd1634a3e3e523ff098b (patch)
tree3e1d3d844987a6f02d406e13f68aa37e3f55ec7e /src/northbridge/amd
parent9c29cfae8cc6214478a0a555e6901779eb19ef54 (diff)
downloadcoreboot-staging-fd611f9c2c8c751069c6cd1634a3e3e523ff098b.zip
coreboot-staging-fd611f9c2c8c751069c6cd1634a3e3e523ff098b.tar.gz
Drop CONFIG_WRITE_HIGH_TABLES
It's been on for all boards per default since several years now and the old code path probably doesn't even work anymore. Let's just have one consistent way of doing things. Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2547 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/amd')
-rw-r--r--src/northbridge/amd/agesa/family10/northbridge.c4
-rw-r--r--src/northbridge/amd/agesa/family12/northbridge.c4
-rw-r--r--src/northbridge/amd/agesa/family14/northbridge.c4
-rw-r--r--src/northbridge/amd/agesa/family15/northbridge.c4
-rw-r--r--src/northbridge/amd/agesa/family15tn/northbridge.c4
-rw-r--r--src/northbridge/amd/amdfam10/northbridge.c7
-rw-r--r--src/northbridge/amd/amdk8/northbridge.c6
-rw-r--r--src/northbridge/amd/gx1/northbridge.c4
-rw-r--r--src/northbridge/amd/gx2/northbridge.c4
-rw-r--r--src/northbridge/amd/lx/northbridge.c4
10 files changed, 1 insertions, 44 deletions
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index cd21d9c..e0c3255 100644
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
@@ -1036,7 +1036,6 @@ static void amdfam10_domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
-#if CONFIG_WRITE_HIGH_TABLES
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
@@ -1048,7 +1047,6 @@ static void amdfam10_domain_set_resources(device_t dev)
printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
(u32)(high_tables_size / 1024), high_tables_base);
}
-#endif
}
basek = mmio_basek;
}
@@ -1063,7 +1061,6 @@ static void amdfam10_domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
-#if CONFIG_WRITE_HIGH_TABLES
printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
i, mmio_basek, basek, limitk);
if (high_tables_base==0) {
@@ -1075,7 +1072,6 @@ static void amdfam10_domain_set_resources(device_t dev)
#endif
high_tables_size = HIGH_MEMORY_SIZE;
}
-#endif
}
#if CONFIG_GFXUMA
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index 1467fdc..2ef5563 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -722,7 +722,6 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n");
ram_resource(dev, idx, basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
-#if CONFIG_WRITE_HIGH_TABLES
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
@@ -735,7 +734,6 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n");
(u32)(high_tables_size / 1024),
high_tables_base);
}
-#endif
}
basek = mmio_basek;
@@ -751,7 +749,6 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n");
ram_resource(dev, (idx | 0), basek, sizek);
idx += 0x10;
-#if CONFIG_WRITE_HIGH_TABLES
printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
0, mmio_basek, basek, limitk);
if (high_tables_base==0) {
@@ -764,7 +761,6 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n");
#endif
high_tables_size = HIGH_MEMORY_SIZE;
}
-#endif
}
printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek);
printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n",
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index c1685ec..3d46ad7 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -716,7 +716,6 @@ static void domain_set_resources(device_t dev)
pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
-#if CONFIG_WRITE_HIGH_TABLES
if (high_tables_base == 0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
@@ -728,7 +727,6 @@ static void domain_set_resources(device_t dev)
printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
(u32)(high_tables_size / 1024), high_tables_base);
}
-#endif
}
basek = mmio_basek;
@@ -743,7 +741,6 @@ static void domain_set_resources(device_t dev)
ram_resource(dev, (idx | 0), basek, sizek);
idx += 0x10;
-#if CONFIG_WRITE_HIGH_TABLES
printk(BIOS_DEBUG,
"%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0,
mmio_basek, basek, limitk);
@@ -757,7 +754,6 @@ static void domain_set_resources(device_t dev)
#endif
high_tables_size = HIGH_MEMORY_SIZE;
}
-#endif
}
printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek);
printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n",
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index 5cd76a3..36e1499 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -807,7 +807,6 @@ static void domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
-#if CONFIG_WRITE_HIGH_TABLES
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
@@ -819,7 +818,6 @@ static void domain_set_resources(device_t dev)
printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
(u32)(high_tables_size / 1024), high_tables_base);
}
-#endif
}
basek = mmio_basek;
}
@@ -834,7 +832,6 @@ static void domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
-#if CONFIG_WRITE_HIGH_TABLES
printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
i, mmio_basek, basek, limitk);
if (high_tables_base==0) {
@@ -846,7 +843,6 @@ static void domain_set_resources(device_t dev)
#endif
high_tables_size = HIGH_MEMORY_SIZE;
}
-#endif
}
#if CONFIG_GFXUMA
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index 144dde7..90f8345 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -793,7 +793,6 @@ static void domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
-#if CONFIG_WRITE_HIGH_TABLES
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
@@ -805,7 +804,6 @@ static void domain_set_resources(device_t dev)
printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
(u32)(high_tables_size / 1024), high_tables_base);
}
-#endif
}
basek = mmio_basek;
}
@@ -820,7 +818,6 @@ static void domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
-#if CONFIG_WRITE_HIGH_TABLES
printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
i, mmio_basek, basek, limitk);
if (high_tables_base==0) {
@@ -832,7 +829,6 @@ static void domain_set_resources(device_t dev)
#endif
high_tables_size = HIGH_MEMORY_SIZE;
}
-#endif
}
#if CONFIG_GFXUMA
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index aabbae2..875f462 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -842,9 +842,7 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id)
#endif
-#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
-#endif
static void setup_uma_memory(void)
{
@@ -1039,7 +1037,7 @@ static void amdfam10_domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
-#if CONFIG_WRITE_HIGH_TABLES
+
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
@@ -1051,7 +1049,6 @@ static void amdfam10_domain_set_resources(device_t dev)
printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
HIGH_MEMORY_SIZE / 1024, high_tables_base);
}
-#endif
}
#if !CONFIG_AMDMCT
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
@@ -1077,7 +1074,6 @@ static void amdfam10_domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
-#if CONFIG_WRITE_HIGH_TABLES
printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
i, mmio_basek, basek, limitk);
if (high_tables_base==0) {
@@ -1089,7 +1085,6 @@ static void amdfam10_domain_set_resources(device_t dev)
#endif
high_tables_size = HIGH_MEMORY_SIZE;
}
-#endif
}
#if CONFIG_GFXUMA
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 5ed7762..5c1d97a 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -817,9 +817,7 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id)
}
#endif
-#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
-#endif
static void setup_uma_memory(void)
{
@@ -1044,7 +1042,6 @@ static void amdk8_domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
-#if CONFIG_WRITE_HIGH_TABLES
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA
@@ -1056,7 +1053,6 @@ static void amdk8_domain_set_resources(device_t dev)
printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
HIGH_MEMORY_SIZE / 1024, high_tables_base);
}
-#endif
}
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
if(reset_memhole)
@@ -1079,7 +1075,6 @@ static void amdk8_domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
-#if CONFIG_WRITE_HIGH_TABLES
printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
i, mmio_basek, basek, limitk);
if (high_tables_base==0) {
@@ -1091,7 +1086,6 @@ static void amdk8_domain_set_resources(device_t dev)
#endif
high_tables_size = HIGH_MEMORY_SIZE;
}
-#endif
}
#if CONFIG_GFXUMA
diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c
index e483263..4547b8d 100644
--- a/src/northbridge/amd/gx1/northbridge.c
+++ b/src/northbridge/amd/gx1/northbridge.c
@@ -64,9 +64,7 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = PCI_DEVICE_ID_CYRIX_PCI_MASTER,
};
-#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
-#endif
static void pci_domain_set_resources(device_t dev)
{
@@ -111,11 +109,9 @@ static void pci_domain_set_resources(device_t dev)
tolmk = tomk;
}
-#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
-#endif
/* Report the memory regions */
idx = 10;
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index 9952374..62de416 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -271,9 +271,7 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = PCI_DEVICE_ID_NS_GX2,
};
-#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
-#endif
static void pci_domain_set_resources(device_t dev)
{
@@ -292,11 +290,9 @@ static void pci_domain_set_resources(device_t dev)
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tomk - 768); /* Systop - 0xc0000 -> KB */
-#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
-#endif
}
assign_resources(dev->link_list);
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index 3a2eb46..5909d13 100644
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -370,9 +370,7 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = PCI_DEVICE_ID_AMD_LXBRIDGE,
};
-#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
-#endif
static void pci_domain_set_resources(device_t dev)
{
@@ -391,11 +389,9 @@ static void pci_domain_set_resources(device_t dev)
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tomk - 768); // Systop - 0xc0000 -> KB
-#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
-#endif
}
assign_resources(dev->link_list);
OpenPOWER on IntegriCloud