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| author | WANG Siyuan <wangsiyuanbuaa@gmail.com> | 2015-06-12 16:41:50 +0800 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-06-22 22:27:14 +0200 |
| commit | d3deecdd9c5c0a8031f2ea9d6c90e0997f123d93 (patch) | |
| tree | 4a0b83584f206b625c7900b548628835f32f73b3 /src/northbridge/amd | |
| parent | d1da74ff9d61f42432eb78e76a11903afcf68b7b (diff) | |
| download | coreboot-staging-d3deecdd9c5c0a8031f2ea9d6c90e0997f123d93.zip coreboot-staging-d3deecdd9c5c0a8031f2ea9d6c90e0997f123d93.tar.gz | |
AMD OemS3Save: refactor for Merlin Falcon
Merlin Falcon(Carrizo) replaces struct AMD_S3SAVE_PARAMS
with struct AMD_RTB_PARAMS and replaces AMD_S3_PARAMS with
S3_DATA_BLOCK.
Change-Id: If074a8de95d82130d29b2e3cfbd7e35cdb9b929d
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10526
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/agesa/agesawrapper.h | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/oem_s3.c | 8 |
2 files changed, 8 insertions, 2 deletions
diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h index eb1a59c..7e58e79 100644 --- a/src/northbridge/amd/agesa/agesawrapper.h +++ b/src/northbridge/amd/agesa/agesawrapper.h @@ -74,6 +74,6 @@ extern const struct OEM_HOOK OemCustomize; /* For suspend-to-ram support. */ AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams); AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3LateParams); -AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams); +AGESA_STATUS OemS3Save(void *vS3SaveParams); #endif /* _AGESAWRAPPER_H_ */ diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c index dfc1ebc..77bab67 100644 --- a/src/northbridge/amd/agesa/oem_s3.c +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -115,9 +115,15 @@ static int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len) #endif } -AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams) +AGESA_STATUS OemS3Save(void *vS3SaveParams) { +#if IS_ENABLED(CONFIG_CPU_AMD_PI_00660F01) + AMD_RTB_PARAMS *S3SaveParams = (AMD_RTB_PARAMS *)vS3SaveParams; + S3_DATA_BLOCK *dataBlock = &S3SaveParams->S3DataBlock; +#else + AMD_S3SAVE_PARAMS *S3SaveParams = (AMD_S3SAVE_PARAMS *)vS3SaveParams; AMD_S3_PARAMS *dataBlock = &S3SaveParams->S3DataBlock; +#endif u8 MTRRStorage[S3_DATA_MTRR_SIZE]; u32 MTRRStorageSize = 0; u32 pos, size; |
