diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-02-20 13:13:35 -0600 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-03-07 22:50:07 +0100 |
| commit | b6fa61a1216cc48a199335d9414698401d20dbf2 (patch) | |
| tree | 5cf3aab0a983640fe045abca6eddaaa47d2467ff /src/northbridge/amd | |
| parent | 982473536bd8e698bf91f23d8b9a237c0ff29cac (diff) | |
| download | coreboot-staging-b6fa61a1216cc48a199335d9414698401d20dbf2.zip coreboot-staging-b6fa61a1216cc48a199335d9414698401d20dbf2.tar.gz | |
northbridge/amd/amdmct: Fix burst write depth on K10 rev. D and later
The BKDG for K10 revision D and later processors recommends a smaller
MCT burst write queue depth when using unganged memory.
TEST: Booted ASUS KFSN4-DRE with both Opteron 8356 and Opteron 2431
processors.
Change-Id: I36718d4972c9d2d0bdd3274191503b5fcd803f15
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8500
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mct_d.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 7c7550d..bf832da 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -749,7 +750,12 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, } while (!(val & (1 << Dr_MemClrStatus))); } - val = 0x0FE40FC0; // BKDG recommended + /* Implement BKDG Rev 3.62 recommendations */ + val = 0x0FE40F80; + if (!(mctGetLogicalCPUID(0) & AMD_FAM10_LT_D) && mctGet_NVbits(NV_Unganged)) + val |= (0x18 << 2); + else + val |= (0x10 << 2); val |= MCCH_FlushWrOnStpGnt; // Set for S3 Set_NB32(dev, 0x11C, val); } |
