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author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2015-01-04 21:33:39 +1100 |
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committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2015-01-06 01:51:42 +0100 |
commit | 77757c22b9eede92234d07d65a23fdf4b970c8cf (patch) | |
tree | 29949ed8cfac9c5c9b2cf4c8071c74690411d32d /src/mainboard/lippert | |
parent | d76ac6349df0147b9d8f7f09f8bb80343ecfb5e6 (diff) | |
download | coreboot-staging-77757c22b9eede92234d07d65a23fdf4b970c8cf.zip coreboot-staging-77757c22b9eede92234d07d65a23fdf4b970c8cf.tar.gz |
mainboard/*/romstage.c: Sanitize system header inclusions
Fix system include paths to be consistent. Chipset support is
part of the Coreboot 'system' and hence 'non-local' (i.e., in
the same directory or context). One possible product of this, is
to perhaps allow future work to do pre-compiled headers (PCH) on
the buildbot for faster build times. However, this currently just
makes mainboard's consistent.
Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8085
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard/lippert')
-rw-r--r-- | src/mainboard/lippert/frontrunner-af/romstage.c | 8 | ||||
-rw-r--r-- | src/mainboard/lippert/frontrunner/romstage.c | 8 | ||||
-rw-r--r-- | src/mainboard/lippert/hurricane-lx/romstage.c | 8 | ||||
-rw-r--r-- | src/mainboard/lippert/literunner-lx/romstage.c | 8 | ||||
-rw-r--r-- | src/mainboard/lippert/roadrunner-lx/romstage.c | 8 | ||||
-rw-r--r-- | src/mainboard/lippert/spacerunner-lx/romstage.c | 8 | ||||
-rw-r--r-- | src/mainboard/lippert/toucan-af/romstage.c | 8 |
7 files changed, 28 insertions, 28 deletions
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index d21a565..0f718f2 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -32,15 +32,15 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" #include "cbmem.h" -#include "cpu/amd/mtrr.h" -#include "cpu/amd/agesa/s3_resume.h" +#include <cpu/amd/mtrr.h> +#include <cpu/amd/agesa/s3_resume.h> #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c index 3be4eb3..f86d558 100644 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ b/src/mainboard/lippert/frontrunner/romstage.c @@ -6,10 +6,10 @@ #include <console/console.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/gx2def.h> -#include "southbridge/amd/cs5535/cs5535.h" +#include <southbridge/amd/cs5535/cs5535.h> #include "southbridge/amd/cs5535/early_smbus.c" #include "southbridge/amd/cs5535/early_setup.c" @@ -62,7 +62,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return (address < sizeof(spdbytes)) ? spdbytes[address] : 0xFF; } -#include "northbridge/amd/gx2/raminit.h" +#include <northbridge/amd/gx2/raminit.h> #include "northbridge/amd/gx2/pll_reset.c" #include "northbridge/amd/gx2/raminit.c" #include "lib/generic_sdram.c" diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 416a8fb..8e802f3 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -27,16 +27,16 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 8b48640..9199772 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -28,15 +28,15 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 4d8a6fd..dc503ed 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -27,16 +27,16 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 3c25c08..2a22140 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -28,15 +28,15 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index e655f9a..415cdbe 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -32,16 +32,16 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" #include "cbmem.h" -#include "cpu/amd/mtrr.h" -#include "cpu/amd/agesa/s3_resume.h" +#include <cpu/amd/mtrr.h> +#include <cpu/amd/agesa/s3_resume.h> #define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1) |