Changelog:

* src/cpu/amd/model_lx/model_lx_init.c
  L2 cache initialization removed (moved to northbridge.c)
* src/include/cpu/amd/lxdef.h 
  more checked values
* src/northbridge/amd/lx/northbridge.c
  L2 cache initialization added
  cpubug() commented out
* src/northbridge/amd/lx/raminit.c
  empty function sdram_set_registers() is in use, don't remove
* src/mainboard/artecgroup/dbe61/Config.lb
  irqmap changes
* src/mainboard/artecgroup/dbe61/irq_tables.c
  tentative changes to irq table (currently not in use)
* src/mainboard/artecgroup/dbe61/mainboard.c
  irq assigned manually to NIC
* src/mainboard/artecgroup/dbe61/Options.lb
  gcc 4.0 is OK
* targets/artecgroup/dbe61/Config.lb
  64K for VSA is OK at moment
 
Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee>
Signed-off-by: Andrei Birjukov <andrei.birjukov@artecdesign.ee>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 37 insertions, 8 deletions

diff --git a/src/mainboard/artecgroup/dbe61/irq_tables.c b/src/mainboard/artecgroup/dbe61/irq_tables.c
index 636f129..4322e20 100644
--- a/src/mainboard/artecgroup/dbe61/irq_tables.c
+++ b/src/mainboard/artecgroup/dbe61/irq_tables.c
@@ -7,24 +7,53 @@
 
 #include <arch/pirq_routing.h>
 
-const struct irq_routing_table intel_irq_routing_table = {
+#define ID_SLOT_PCI_NET		1			// ThinCan ethernet
+#define ID_SLOT_PCI_RSVD1	2           // reserved entry 1
+#define ID_SLOT_PCI_RSVD3	3           // reserved entry 2
+#define ID_SLOT_PCI_RSVD2	4			// reserved entry 3
+#define ID_EMBED_PCI		0xff		// onboard PCI device
+
+// CS5535 PCI INT[A-D] Interrupt Routing lines.
+#define NO_CONNECT			0			// not used
+#define CS_PCI_INTA			1			// PCI INTA
+#define CS_PCI_INTB			2			// PCI INTB
+#define CS_PCI_INTC			3			// PCI INTC
+#define CS_PCI_INTD			4			// PCI INTD
+
+// IRQ bitmap reference line	FEDCBA9876543210
+//								0000110000100000b
+#define PCI_IRQ					0xc20	// PCI allowed IRQs here
+
+const struct irq_routing_table intel_irq_routing_table = 
+{
 	PIRQ_SIGNATURE,  /* u32 signature */
 	PIRQ_VERSION,    /* u16 version   */
-	32+16*2,	 /* there can be total 2 devices on the bus */
+	32+16*6,		/* there can be total 2 devices on the bus */
 	0x00,		 /* Where the interrupt router lies (bus) */
 	(0x12<<3)|0x0,   /* Where the interrupt router lies (dev) */
-	0x800,		 /* IRQs devoted exclusively to PCI usage */
-	0x1078,		 /* Vendor */
-	0x2,		 /* Device */
-	0,		 /* Crap (miniport) */
+	0x0800,			/* IRQs devoted exclusively to PCI usage */
+	0x1022,			/* Vendor */
+	0x208f,			/* Device */
+	0x00000000,		/* Crap (miniport) */
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
 	0xdf,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
 	{
 		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x0e<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
-		{0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},
+		// Geode GX3 Host Bridge and VGA Graphics
+		{0, 0x01<<3, {{CS_PCI_INTA, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}}, ID_EMBED_PCI, 0x0},
+		// Realtek RTL8100/8139 Network Controller
+		{0, 0x0d<<3, {{CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}}, ID_SLOT_PCI_NET, 0x0},
+		// Reserved for future extensions
+		{0, 0x0c<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_SLOT_PCI_RSVD1, 0x0},
+		// Geode CS5535/CS5536 IO Companion: USB controllers, IDE, Audio.
+		{0, 0x0f<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_EMBED_PCI, 0x0},
+		// Reserved for future extensions
+		{0, 0x0e<<3, {{CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}}, ID_SLOT_PCI_RSVD2, 0x0},
+		// Reserved for future extensions
+		{0, 0x0b<<3, {{CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}}, ID_SLOT_PCI_RSVD3, 0x0}
 	}
 };
+
 unsigned long write_pirq_routing_table(unsigned long addr)
 {
         return copy_pirq_routing_table(addr);