On behalf of AMD:

Drop AMD prototype mainboards that were for internal testing & 
validation use only. 

Note: These boards could never be purchased. No reasons to worry.
Questions welcome via private mail.

Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2609 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

11 files changed, 0 insertions, 1186 deletions

diff --git a/src/mainboard/amd/serenade/Config.lb b/src/mainboard/amd/serenade/Config.lb
deleted file mode 100644
index c1f233d..0000000
--- a/src/mainboard/amd/serenade/Config.lb
+++ /dev/null
@@ -1,215 +0,0 @@
-##
-## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-	default ROM_SECTION_SIZE   = FALLBACK_SIZE
-	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-	default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The linuxBIOS bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of linuxBIOS will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
-arch i386 end 
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
-#object reset.o
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(MAINBOARD)/failover.c ./romcc" 
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(MAINBOARD)/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
-	action	"./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-	action	"./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit linuxBIOS entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where linuxBIOS is entered)
-##
-if USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of linuxBIOS startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
- 
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/amd/amdk8/root_complex
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8 # mc
-			device pci 18.0 on end # LDT 0 
-			device pci 18.0 on end # LDT1
-			device pci 18.0 on     # LDT2
-				chip southbridge/amd/amd8131
-					# the on/off keyword is mandatory
-					device pci 0.0 on end
-					device pci 0.1 on end
-					device pci 1.0 on end
-					device pci 1.1 on end
-				end
-				chip southbridge/amd/amd8111
-					# this "device pci 0.0" is the parent the next one
-					# PCI bridge
-					device pci 0.0 on
-						device pci 0.0 on end
-						device pci 0.1 on end
-						device pci 0.2 on end
-						device pci 1.0 off end
-					end
-					device pci 1.0 on
-						chip superio/winbond/w83627hf
-							device	pnp 2e.0 on  # Floppy 
-								 io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 off  # Parallel Port
-								 io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.2 on # Com 1
-								 io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.3 off # Com 2
-								 io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 2e.5 on  # Keyboard
-								 io 0x60 = 0x60
-								 io 0x62 = 0x64
-								irq 0x70 = 1
-								irq 0x72 = 12
-							end
-							device pnp 2e.6 off end # CIR
-							device pnp 2e.7 off end # GAM_MIDI_GIPO1
-							device pnp 2e.8 off end # GPIO2
-							device pnp 2e.9 off end # GPIO3
-							device pnp 2e.a off end # ACPI
-							device pnp 2e.b on      # HW Monitor
-								 io 0x60 = 0x290
-							end 
-						end
-					end
-					device pci 1.1 on end
-					device pci 1.2 on end
-					device pci 1.3 on end
-					device pci 1.5 off end
-					device pci 1.6 off end
-                                        register "ide0_enable" = "1"
-                                        register "ide1_enable" = "1"
-				end
-			end # device pci 18.0 
-			
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end
-		chip northbridge/amd/amdk8
-			device pci 19.0 on end
-			device pci 19.0 on end
-			device pci 19.0 on end
-			device pci 19.1 on end
-			device pci 19.2 on end
-			device pci 19.3 on end
-		end
-	end
-	device apic_cluster 0 on
-		chip cpu/amd/socket_940
-			device apic 0 on end
-		end
-		chip cpu/amd/socket_940
-			device apic 1 on end
-		end
-	end
-end
-
diff --git a/src/mainboard/amd/serenade/Options.lb b/src/mainboard/amd/serenade/Options.lb
deleted file mode 100644
index 20e2615..0000000
--- a/src/mainboard/amd/serenade/Options.lb
+++ /dev/null
@@ -1,206 +0,0 @@
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROM_PAYLOAD_START
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD
-uses LINUXBIOS_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses OBJCOPY
-
-uses CONFIG_USE_INIT
-
-###
-### Build options
-###
-
-##
-## ROM_SIZE is the size of boot ROM that this board will use.
-##
-default ROM_SIZE=524288
-
-##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default FALLBACK_SIZE=0x40000
-
-##
-## Build code for the fallback boot
-##
-default HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from linuxBIOS
-##
-default HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=9
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default HAVE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default HAVE_OPTION_TABLE=1
-
-##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
-##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-default CONFIG_MAX_PHYSICAL_CPUS=2
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default MAINBOARD_PART_NUMBER="SERENADE"
-default MAINBOARD_VENDOR="AMD"
-
-###
-### LinuxBIOS layout values
-###
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-default ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-
-##
-## LinuxBIOS C code runs at this location in RAM
-##
-default _RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
-
-# Select the serial console base port
-default TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
-
-##
-### Select the linuxBIOS loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/amd/serenade/auto.c b/src/mainboard/amd/serenade/auto.c
deleted file mode 100644
index 72b0648..0000000
--- a/src/mainboard/amd/serenade/auto.c
+++ /dev/null
@@ -1,218 +0,0 @@
-#define ASSEMBLY 1
-#define DEFAULT_CONSOLE_LOGLEVEL 8
-#define MAXIMUM_CONSOLE_LOGLEVEL 8
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-static void hard_reset(void)
-{
-	set_bios_reset();
-
-	/* enable cf9 */
-	pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
-	/* reset */
-	outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-	set_bios_reset();
-	pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
-}
-
-/*
- * GPIO16 of 8111 will control H0_MEMRESET_L
- * GPIO17 of 8111 will control H1_MEMRESET_L
- */
-static void memreset_setup(void)
-{
-	if (is_cpu_pre_c0()) {
-		/* Set the memreset low */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
-		/* Ensure the BIOS has control of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
-	} else {
-		/* Ensure the CPU has controll of the memory lines */
-		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
-	}
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-	if (is_cpu_pre_c0()) {
-		udelay(800);
-		/* Set memreset_high */
-		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
-		udelay(90);
-	}
-}
-
-static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
-{
-	/* Routing Table Node i 
-	 *
-	 * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c 
-	 *  i:    0,    1,    2,    3,    4,    5,    6,    7
-	 *
-	 * [ 0: 3] Request Route
-	 *     [0] Route to this node
-	 *     [1] Route to Link 0
-	 *     [2] Route to Link 1
-	 *     [3] Route to Link 2
-	 * [11: 8] Response Route
-	 *     [0] Route to this node
-	 *     [1] Route to Link 0
-	 *     [2] Route to Link 1
-	 *     [3] Route to Link 2
-	 * [19:16] Broadcast route
-	 *     [0] Route to this node
-	 *     [1] Route to Link 0
-	 *     [2] Route to Link 1
-	 *     [3] Route to Link 2
-	 */
-
-	uint32_t ret = 0x00010101; /* default row entry */
-
-        /* CPU0 LDT0 <-> LDT0 CPU1 */
-	static const unsigned int rows_2p[2][2] = {
-		{ 0x00030101, 0x00010202 },
-		{ 0x00010202, 0x00030101 }
-	};
-
-	if (maxnodes > 2) {
-		print_debug("this mainboard is only designed for 2 cpus\r\n");
-		maxnodes = 2;
-	}
-
-	if (!(node >= maxnodes || row >= maxnodes)) {
-		ret = rows_2p[node][row];
-	}
-
-	return ret;
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "sdram/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define FIRST_CPU  1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(unsigned long bist)
-{
-	static const struct mem_controller cpu[] = {
-#if FIRST_CPU
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x18, 0),
-			.f1 = PCI_DEV(0, 0x18, 1),
-			.f2 = PCI_DEV(0, 0x18, 2),
-			.f3 = PCI_DEV(0, 0x18, 3),
-			.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
-			.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
-		},
-#endif
-#if SECOND_CPU
-		{
-			.node_id = 1,
-			.f0 = PCI_DEV(0, 0x19, 0),
-			.f1 = PCI_DEV(0, 0x19, 1),
-			.f2 = PCI_DEV(0, 0x19, 2),
-			.f3 = PCI_DEV(0, 0x19, 3),
-			.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
-			.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
-		},
-#endif
-	};
-
-	int needs_reset;
-	unsigned nodeid;
-	if (bist == 0) {
-	    	k8_init_and_stop_secondaries();
-	}
-	/* Setup the console */
-        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-	uart_init();
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-#if 0
-	print_pci_devices();
-#endif
-
-	setup_amd_serenade_resource_map();
-	needs_reset = setup_coherent_ht_domain();
-	/* non-coherent HT is on LDT2 */
-	needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xC0);
-	if (needs_reset) {
-		print_info("ht reset -\r\n");
-		soft_reset();
-	}
-
-#if 1
-	print_pci_devices();
-#endif
-
-	enable_smbus();
-
-#if 0
-	dump_spd_registers(&cpu[0]);
-#endif
-
-	memreset_setup();
-	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
-
-#if 0
-	dump_pci_devices();
-#endif
-
-	print_pci_devices();
-
-#if 0
-	dump_pci_device(PCI_DEV(0, 0x18, 2));
-#endif
-
-#if 0
-	/* Check the first 1M */
-	ram_check(0x00000000, 0x001000000);
-#endif
-
-}
diff --git a/src/mainboard/amd/serenade/chip.h b/src/mainboard/amd/serenade/chip.h
deleted file mode 100644
index 9f24477..0000000
--- a/src/mainboard/amd/serenade/chip.h
+++ /dev/null
@@ -1,5 +0,0 @@
-extern struct chip_operations mainboard_amd_serenade_ops;
-
-struct mainboard_amd_serenade_config {
-	int nothing;
-};
diff --git a/src/mainboard/amd/serenade/cmos.layout b/src/mainboard/amd/serenade/cmos.layout
deleted file mode 100644
index 5eb88b9..0000000
--- a/src/mainboard/amd/serenade/cmos.layout
+++ /dev/null
@@ -1,98 +0,0 @@
-entries
-
-#start-bit length  config config-ID    name
-#0            8       r       0        seconds
-#8            8       r       0        alarm_seconds
-#16           8       r       0        minutes
-#24           8       r       0        alarm_minutes
-#32           8       r       0        hours
-#40           8       r       0        alarm_hours
-#48           8       r       0        day_of_week
-#56           8       r       0        day_of_month
-#64           8       r       0        month
-#72           8       r       0        year
-#80           4       r       0        rate_select
-#84           3       r       0        REF_Clock
-#87           1       r       0        UIP
-#88           1       r       0        auto_switch_DST
-#89           1       r       0        24_hour_mode
-#90           1       r       0        binary_values_enable
-#91           1       r       0        square-wave_out_enable
-#92           1       r       0        update_finished_enable
-#93           1       r       0        alarm_interrupt_enable
-#94           1       r       0        periodic_interrupt_enable
-#95           1       r       0        disable_clock_updates
-#96         288       r       0        temporary_filler
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-385          1       e       4        last_boot
-386          1       e       1        ECC_memory
-388          4       r       0        reboot_bits
-392          3       e       5        baud_rate
-395          1       e       1        hw_scrubber
-396          1       e       1        interleave_chip_selects
-397          2       e       8        max_mem_clock
-399	     1	     e	     2	      dual_core
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-416          4       e       7        boot_first
-420          4       e       7        boot_second
-424          4       e       7        boot_third
-428          4       h       0        boot_index
-432	     8       h       0        boot_countdown
-440          4       e       9        slow_cpu
-444          1       e       1        nmi
-445          1       e       1        iommu
-728        256       h       0        user_data
-984         16       h       0        check_sum
-# Reserve the extended AMD configuration registers
-1000        24       r       0        reserved_memory
-
-
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-5     0     115200
-5     1     57600
-5     2     38400
-5     3     19200
-5     4     9600
-5     5     4800
-5     6     2400
-5     7     1200
-6     6     Notice
-6     7     Info
-6     8     Debug
-6     9     Spew
-7     0     Network
-7     1     HDD
-7     2     Floppy
-7     8     Fallback_Network
-7     9     Fallback_HDD
-7     10    Fallback_Floppy
-#7     3     ROM
-8     0     DDR400
-8     1     DDR333
-8     2     DDR266
-8     3     DDR200
-9     0     off
-9     1     87.5%
-9     2     75.0%
-9     3     62.5%
-9     4     50.0%
-9     5     37.5%
-9     6     25.0%
-9     7     12.5%
-
-checksums
-
-checksum 392 983 984
-
-
diff --git a/src/mainboard/amd/serenade/failover.c b/src/mainboard/amd/serenade/failover.c
deleted file mode 100644
index 1738e90..0000000
--- a/src/mainboard/amd/serenade/failover.c
+++ /dev/null
@@ -1,68 +0,0 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
-	unsigned nodeid;
-
-	/* Make cerain my local apic is useable */
-	enable_lapic();
-
-	nodeid = lapicid() & 0xf;
-
-	/* Is this a cpu only reset? */
-	if (early_mtrr_init_detected()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	/* Is this a secondary cpu? */
-	if (!boot_cpu()) {
-		if (last_boot_normal()) {
-			goto normal_image;
-		} else {
-			goto fallback_image;
-		}
-	}
-	
-
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain();
-	
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a deliberate reset by the bios */
-	if (bios_reset_detected() && last_boot_normal()) {
-		goto normal_image;
-	}
-	/* This is the primary cpu how should I boot? */
-	else if (do_normal_boot()) {
-		goto normal_image;
-	}
-	else {
-		goto fallback_image;
-	}
- normal_image:
-	asm volatile ("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
- fallback_image:
-	return bist;
-}
diff --git a/src/mainboard/amd/serenade/irq_tables.c b/src/mainboard/amd/serenade/irq_tables.c
deleted file mode 100644
index f340a2d..0000000
--- a/src/mainboard/amd/serenade/irq_tables.c
+++ /dev/null
@@ -1,61 +0,0 @@
-#include <arch/pirq_routing.h>
-#include <device/pci.h>
-
-#define IRQ_SLOT_COUNT 12
-#define IRQ_ROUTER_BUS		0
-#define IRQ_ROUTER_DEVFN	PCI_DEVFN(4,3)
-#define IRQ_ROUTER_VENDOR	0x1022
-#define IRQ_ROUTER_DEVICE	0x746b
-
-#define AVAILABLE_IRQS 0xdef8
-#define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \
-	{ bus, (dev<<3)|fn, {{ linka, AVAILABLE_IRQS}, { linkb, AVAILABLE_IRQS}, \
-	{linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0}
-
-/*  Each IRQ_SLOT entry consists of:
- *  bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu  
- */
-
-const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,		/* u32 signature */
-	PIRQ_VERSION,           /* u16 version   */
-	32+16*IRQ_SLOT_COUNT,	/* there can be total IRQ_SLOT_COUNT table entries */
-	IRQ_ROUTER_BUS,		/* Where the interrupt router lies (bus) */
-	IRQ_ROUTER_DEVFN,	/* Where the interrupt router lies (dev) */
-	0x00,			/* IRQs devoted exclusively to PCI usage */
-	IRQ_ROUTER_VENDOR,	/* Vendor */
-	IRQ_ROUTER_DEVICE,	/* Device */
-	0x00,			/* Crap (miniport) */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x34,			/*  u8 checksum , mod 256 checksum must give zero */
-	{	/* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
-		/* Northbridge, Node 0 */
-		IRQ_SLOT(0x0, 0x00,0x18,0x0, 0,0,0,0),
-		/* AMD-8131 PCI-X Bridge */
-		IRQ_SLOT(0x0, 0x01,0x01,0x0, 0,0,0,0),
-		/* Onboard LSI SCSI Controller */
-		IRQ_SLOT(0x0, 0x02,0x02,0x0, 3,0,0,0),
-		/* Onboard Broadcom NICs */
-		IRQ_SLOT(0x0, 0x02,0x01,0x0, 1,2,0,0),
-		/* AMD-8131 PCI-X Bridge */
-		IRQ_SLOT(0x0, 0x01,0x02,0x0, 0,0,0,0),
-		/* PCI Slot 1-2 */
-		IRQ_SLOT(0x1, 0x03,0x03,0x0, 1,2,3,4),
-		IRQ_SLOT(0x2, 0x03,0x04,0x0, 2,3,4,1),
-		/* AMD-8111 PCI Bridge */
-		IRQ_SLOT(0x0, 0x01,0x03,0x0, 0,0,0,0),
-		/* USB Controller */
-		IRQ_SLOT(0x0, 0x04,0x00,0x0, 0,0,0,4),
-		/* ATI Rage XL VGA */
-		IRQ_SLOT(0x0, 0x04,0x05,0x0, 1,0,0,0),
-		/* AMD-8111 LPC Dridge */
-		IRQ_SLOT(0x0, 0x01,0x04,0x0, 0,0,0,0),
-		/* Northbridge, Node 1 */
-		IRQ_SLOT(0x0, 0x00,0x19,0x0, 0,0,0,0),
-
-	}
-};
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-        return copy_pirq_routing_table(addr);
-}
diff --git a/src/mainboard/amd/serenade/mainboard.c b/src/mainboard/amd/serenade/mainboard.c
deleted file mode 100644
index d0c9112..0000000
--- a/src/mainboard/amd/serenade/mainboard.c
+++ /dev/null
@@ -1,7 +0,0 @@
-#include <device/device.h>
-#include "chip.h"
-
-struct chip_operations mainboard_amd_serenade_ops = {
-	CHIP_NAME("AMD Serenade Mainboard")
-};
-
diff --git a/src/mainboard/amd/serenade/mptable.c b/src/mainboard/amd/serenade/mptable.c
deleted file mode 100644
index b00eb2b..0000000
--- a/src/mainboard/amd/serenade/mptable.c
+++ /dev/null
@@ -1,175 +0,0 @@
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-
-void *smp_write_config_table(void *v)
-{
-	static const char sig[4] = "PCMP";
-	static const char oem[8] = "AMD     ";
-	static const char productid[12] = "Serenade   ";
-	struct mp_config_table *mc;
-
-	unsigned char bus_num;
-	unsigned char bus_isa;
-	unsigned char bus_8111_0;
-	unsigned char bus_8111_1;
-	unsigned char bus_8131_1;
-	unsigned char bus_8131_2;
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-	memset(mc, 0, sizeof(*mc));
-
-	memcpy(mc->mpc_signature, sig, sizeof(sig));
-	mc->mpc_length = sizeof(*mc); /* initially just the header */
-	mc->mpc_spec = 0x04;
-	mc->mpc_checksum = 0; /* not yet computed */
-	memcpy(mc->mpc_oem, oem, sizeof(oem));
-	memcpy(mc->mpc_productid, productid, sizeof(productid));
-	mc->mpc_oemptr = 0;
-	mc->mpc_oemsize = 0;
-	mc->mpc_entry_count = 0; /* No entries yet... */
-	mc->mpc_lapic = LAPIC_ADDR;
-	mc->mpe_length = 0;
-	mc->mpe_checksum = 0;
-	mc->reserved = 0;
-
-	smp_write_processors(mc);
-
-	{
-		device_t dev;
-
-		/* 8111 */
-		dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
-		if (dev) {
-                	bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS);
-			bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-			bus_isa	   = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-			bus_isa++;
-		} else {
-			printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
-			bus_8111_1 = 4;
-			bus_isa = 5;
-		}
-
-		/* 8131-1 */
-		dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
-		if (dev) {
-			bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
-		} else {
-			printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
-			bus_8131_1 = 2;
-		}
-
-		/* 8131-2 */
-		dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
-		if (dev) {
-			bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-		} else {
-			printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
-			bus_8131_2 = 3;
-		}
-	}
-
-	/* define bus and isa numbers */
-	for (bus_num = 0; bus_num < bus_isa; bus_num++) {
-		smp_write_bus(mc, bus_num, "PCI	  ");
-	}
-	smp_write_bus(mc, bus_isa, "ISA	  ");
-
-	/* Legacy IOAPIC #2 */
-	smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
-	{
-		device_t dev;
-		struct resource *res;
-		/* 8131-1 apic #3 */
-		dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
-		if (dev) {
-			res = find_resource(dev, PCI_BASE_ADDRESS_0);
-			if (res) {
-				smp_write_ioapic(mc, 0x03, 0x11, res->base);
-			}
-		}
-		/* 8131-2 apic #4 */
-		dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
- 		if (dev) {
-			res = find_resource(dev, PCI_BASE_ADDRESS_0);
-			if (res) {
-				smp_write_ioapic(mc, 0x04, 0x11, res->base);
-			}
-		}
-	}
-
-	/* ISA backward compatibility interrupts  */
-	smp_write_intsrc(mc, mp_ExtINT,	MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, 0x02, 0x00);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x01, 0x02, 0x01);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, 0x02, 0x02);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x03, 0x02, 0x03);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x04, 0x02, 0x04);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x05, 0x02, 0x05);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x06, 0x02, 0x06);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x07, 0x02, 0x07);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x08, 0x02, 0x08);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x09, 0x02, 0x09);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x0a, 0x02, 0x0a);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x0b, 0x02, 0x0b);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x0c, 0x02, 0x0c);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x0d, 0x02, 0x0d);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x0e, 0x02, 0x0e);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x0f, 0x02, 0x0f);
-
-	/* PCI Ints:	     Type	Polarity    	    Trigger		  	Bus ID      PCIDEVNUM|IRQ  APIC ID PIN# */
-	/* Integrated SMBus 2.0 */
-        smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|3, 0x2, 0x13);
-	/* Integrated AMD AC97 Audio */
-        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|1, 0x2, 0x11);
-
-	/* Integrated AMD USB */
-        smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x00<<2)|3, 0x2, 0x13);
-
-	/* On board ATI Rage XL */
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, 0x2, 0x10);
-
-	/* On board Broadcom nics */
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x3, 0x00);
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x3, 0x01);
-
-	/* On board LSI SCSI */
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, 0x3, 0x02);
-
-	/* PCI Slot 1 PCIX */
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|0, 0x2, 0x10);
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|1, 0x2, 0x11);
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|2, 0x2, 0x12);
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|3, 0x2, 0x13);
-
-	/* PCI Slot 2 PCIX */
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|0, 0x2, 0x11);
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|1, 0x2, 0x12);
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|2, 0x2, 0x13);
-	smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|3, 0x2, 0x10);
-
-	/* Standard local interrupt assignments:
-	 * 		      Type	 Polarity		Trigger			 Bus ID   IRQ	APIC ID	     PIN# */
-	smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x00);
-	smp_write_lintsrc(mc, mp_NMI,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x01);
-
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr);
-	return (unsigned long)smp_write_config_table(v);
-}
-
diff --git a/src/mainboard/amd/serenade/reset.c b/src/mainboard/amd/serenade/reset.c
deleted file mode 100644
index 6395818..0000000
--- a/src/mainboard/amd/serenade/reset.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include "../../../southbridge/amd/amd8111/amd8111_reset.c"
-
-void hard_reset(void)
-{
-	amd8111_hard_reset(0, 2);
-}
diff --git a/src/mainboard/amd/serenade/resourcemap.c b/src/mainboard/amd/serenade/resourcemap.c
deleted file mode 100644
index 2e026d0..0000000
--- a/src/mainboard/amd/serenade/resourcemap.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * AMD Serenade needs a different resource map
- *
- */
-
-static void setup_amd_serenade_resource_map(void)
-{
-	static const unsigned int register_values[] = {
-	/* Careful set limit registers before base registers which contain the enables */
-	/* DRAM Limit i Registers
-	 * F1:0x44 i = 0
-	 * F1:0x4C i = 1
-	 * F1:0x54 i = 2
-	 * F1:0x5C i = 3
-	 * F1:0x64 i = 4
-	 * F1:0x6C i = 5
-	 * F1:0x74 i = 6
-	 * F1:0x7C i = 7
-	 * [ 2: 0] Destination Node ID
-	 *	   000 = Node 0
-	 *	   001 = Node 1
-	 *	   010 = Node 2
-	 *	   011 = Node 3
-	 *	   100 = Node 4
-	 *	   101 = Node 5
-	 *	   110 = Node 6
-	 *	   111 = Node 7
-	 * [ 7: 3] Reserved
-	 * [10: 8] Interleave select
-	 *	   specifies the values of A[14:12] to use with interleave enable.
-	 * [15:11] Reserved
-	 * [31:16] DRAM Limit Address i Bits 39-24
-	 *	   This field defines the upper address bits of a 40 bit  address
-	 *	   that define the end of the DRAM region.
-	 */
-	PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
-	PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
-	PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
-	PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
-	PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
-	PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
-	PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
-	/* DRAM Base i Registers
-	 * F1:0x40 i = 0
-	 * F1:0x48 i = 1
-	 * F1:0x50 i = 2
-	 * F1:0x58 i = 3
-	 * F1:0x60 i = 4
-	 * F1:0x68 i = 5
-	 * F1:0x70 i = 6
-	 * F1:0x78 i = 7
-	 * [ 0: 0] Read Enable
-	 *	   0 = Reads Disabled
-	 *	   1 = Reads Enabled
-	 * [ 1: 1] Write Enable
-	 *	   0 = Writes Disabled
-	 *	   1 = Writes Enabled
-	 * [ 7: 2] Reserved
-	 * [10: 8] Interleave Enable
-	 *	   000 = No interleave
-	 *	   001 = Interleave on A[12] (2 nodes)
-	 *	   010 = reserved
-	 *	   011 = Interleave on A[12] and A[14] (4 nodes)
-	 *	   100 = reserved
-	 *	   101 = reserved
-	 *	   110 = reserved
-	 *	   111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
-	 * [15:11] Reserved
-	 * [13:16] DRAM Base Address i Bits 39-24
-	 *	   This field defines the upper address bits of a 40-bit address
-	 *	   that define the start of the DRAM region.
-	 */
-	PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
-	/* Memory-Mapped I/O Base and Limit i Registers */
-	/* Base = 0x8000, Limit = 0xffff, Read/Write, DstNode = 0, DstLink = LDT2 */
-	PCI_ADDR(0, 0x18, 1, 0xbc), 0x00000048, 0x00ffff20,
-	PCI_ADDR(0, 0x18, 1, 0xb8), 0x000000f0, 0x00fc0003,
-	/* Base = 0x0a00, Limit = 0x0b00, Read/Write, DstNode = 0, DstLink = LDT2 */
-	PCI_ADDR(0, 0x18, 1, 0xac), 0x00000048, 0x00000b20,
-	PCI_ADDR(0, 0x18, 1, 0xa8), 0x000000f0, 0x00000a03,
-	PCI_ADDR(0, 0x18, 1, 0xb4), 0x00000048, 0x00000000, 
-	PCI_ADDR(0, 0x18, 1, 0xb0), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xac), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xa8), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xa4), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xa0), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x9c), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x8c), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
-
-	/* PCI I/O Base and Limit i Registers */
-	/* Base = 0x0000, Limit = 0x1fff, Read/Write, VAG/ISA enabled,
-	   DstNode = 0, DstLink = LDT2 */
-	PCI_ADDR(0, 0x18, 1, 0xc4), 0xFE000FC8, 0x01fff020,
-	PCI_ADDR(0, 0x18, 1, 0xc0), 0xFE000FCC, 0x00000003,
-	PCI_ADDR(0, 0x18, 1, 0xcc), 0xFE000FC8, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xc8), 0xFE000FCC, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xd4), 0xFE000FC8, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xd0), 0xFE000FCC, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xdc), 0xFE000FC8, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xd8), 0xFE000FCC, 0x00000000,
-
-	/* Config Base and Limit i Registers for Non-coherent HT
-	 * Bus 0x00 - 0xff, DstNode = 0, DstLink = LDT2, Read/Write */
-	PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000FC88, 0xff000203,
-	PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0x00000000,
-        };
-        int max;
-        max = sizeof(register_values)/sizeof(register_values[0]);
-        setup_resource_map(register_values, max);
-}