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author | Zheng Bao <zheng.bao@amd.com> | 2010-03-16 01:42:50 +0000 |
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committer | Zheng Bao <Zheng.Bao@amd.com> | 2010-03-16 01:42:50 +0000 |
commit | dec279fa300243bc3c5afe039a5ff6f1fc3264de (patch) | |
tree | 5c6237726610ac9f493759c522636ca17b5cdcd7 /src/mainboard/amd/mahogany/irq_tables.c | |
parent | 1088bbff4503df7e8507aae45da823268262ca8f (diff) | |
download | coreboot-staging-dec279fa300243bc3c5afe039a5ff6f1fc3264de.zip coreboot-staging-dec279fa300243bc3c5afe039a5ff6f1fc3264de.tar.gz |
1. Features of mahogany.
The code can run on the Mahogany board, which is one of sample boards
made by AMD. Its major features are:
CPU (only K8 system):
* AMD AM2+
* AMD Athlon 64 x2
* AMD Athlon 64 FX
* AMD Athlon 64
* AMD Sempron CPUs
System Chipset:
* RS780E
* SB700
On Board Chipset:
* BIOS - SPI
* Azalia CODEC - Realtek ALC888
* LPC SuperIO - ITE8718F(GX).
* LAN - REALTEK 8111C
* TPM - SLB9635TT1.2
Main Memory:
* DDR II * 4 (Max 4GB)
Expansion Slots:
* PCI Express X16 slot*2 (PCI-E X8 Bus)
* PCI Express X4 Slot*1
Intersil PWM:
* Controller - Intersil 6323
2. The ACPI feature is already added. I suggest that firstly we can test
the board without the ACPI by setting the HAVE_ACPI_TABLE as 0.
With Rev F processor, the HT link can only work in HT1, whose max
frequency is 1GHz.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/mahogany/irq_tables.c')
-rw-r--r-- | src/mainboard/amd/mahogany/irq_tables.c | 119 |
1 files changed, 119 insertions, 0 deletions
diff --git a/src/mainboard/amd/mahogany/irq_tables.c b/src/mainboard/amd/mahogany/irq_tables.c new file mode 100644 index 0000000..be4c32d --- /dev/null +++ b/src/mainboard/amd/mahogany/irq_tables.c @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up + + Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> + +#include <cpu/amd/amdk8_sysconf.h> + +extern void get_bus_conf(void); + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} +extern u8 bus_isa; +extern u8 bus_rs780[8]; +extern u8 bus_sb700[2]; +extern unsigned long sbdn_sb700; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk_info("Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_sb700[0]; + pirq->rtr_devfn = ((sbdn_sb700 + 0x14) << 3) | 4; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, bus_sb700[0], ((sbdn_sb700 + 0x14) << 3) | 4, + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk_info("write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} |