Remaining boards are Kconfig'd now. Whether they work

or not still depends on how close the configuration
options are to what they should be.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 48 insertions, 0 deletions

diff --git a/src/mainboard/amd/db800/Kconfig b/src/mainboard/amd/db800/Kconfig
new file mode 100644
index 0000000..336bb37
--- /dev/null
+++ b/src/mainboard/amd/db800/Kconfig
@@ -0,0 +1,48 @@
+config BOARD_AMD_DB800
+	bool "DB800"
+	select ARCH_X86
+	select CPU_AMD_LX
+	select NORTHBRIDGE_AMD_LX
+	select SOUTHBRIDGE_AMD_CS5536
+	select SUPERIO_WINBOND_W83627HF
+	select HAVE_PIRQ_TABLE
+	select PIRQ_ROUTE
+	select UDELAY_TSC
+	select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+	select USE_DCACHE_RAM
+	select USE_PRINTK_IN_CAR
+
+config MAINBOARD_DIR
+	string
+	default amd/db800
+	depends on BOARD_AMD_DB800
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "DB800"
+	depends on BOARD_AMD_DB800
+
+config HAVE_OPTION_TABLE
+	bool
+	default n
+	depends on BOARD_AMD_DB800
+
+config IRQ_SLOT_COUNT
+	int
+	default 6
+	depends on BOARD_AMD_DB800
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xc8000
+	depends on BOARD_AMD_DB800
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x8000
+	depends on BOARD_AMD_DB800
+
+config RAMBASE
+	hex
+	default 0x4000
+	depends on BOARD_AMD_DB800