diff options
author | Patrick Georgi <patrick@georgi-clan.de> | 2012-05-05 15:29:32 +0200 |
---|---|---|
committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-05-08 00:34:34 +0200 |
commit | e166782f397f7db2c4446c5e120fa30afbde7bdd (patch) | |
tree | fac736e744d9ec6d49e321e63971277e611d2000 /src/cpu | |
parent | fe4221848f86ab97d2c439299826d97e48542404 (diff) | |
download | coreboot-staging-e166782f397f7db2c4446c5e120fa30afbde7bdd.zip coreboot-staging-e166782f397f7db2c4446c5e120fa30afbde7bdd.tar.gz |
Clean up #ifs
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} +
Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} +
Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} +
Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} +
(and some manual changes to fix false positives)
Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1004
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>
Diffstat (limited to 'src/cpu')
-rw-r--r-- | src/cpu/amd/agesa/family10/model_10_init.c | 4 | ||||
-rw-r--r-- | src/cpu/amd/agesa/family12/model_12_init.c | 4 | ||||
-rw-r--r-- | src/cpu/amd/agesa/family14/model_14_init.c | 6 | ||||
-rw-r--r-- | src/cpu/amd/agesa/family15/model_15_init.c | 4 | ||||
-rw-r--r-- | src/cpu/amd/car/post_cache_as_ram.c | 10 | ||||
-rw-r--r-- | src/cpu/amd/dualcore/dualcore.c | 2 | ||||
-rw-r--r-- | src/cpu/amd/model_10xxx/init_cpus.c | 10 | ||||
-rw-r--r-- | src/cpu/amd/model_10xxx/model_10xxx_init.c | 4 | ||||
-rw-r--r-- | src/cpu/amd/model_fxx/init_cpus.c | 14 | ||||
-rw-r--r-- | src/cpu/amd/model_fxx/model_fxx_init.c | 20 | ||||
-rw-r--r-- | src/cpu/amd/model_fxx/model_fxx_update_microcode.c | 8 | ||||
-rw-r--r-- | src/cpu/amd/model_fxx/powernow_acpi.c | 2 | ||||
-rw-r--r-- | src/cpu/amd/model_fxx/processor_name.c | 12 | ||||
-rw-r--r-- | src/cpu/amd/mtrr/amd_mtrr.c | 4 | ||||
-rw-r--r-- | src/cpu/intel/hyperthreading/intel_sibling.c | 2 | ||||
-rw-r--r-- | src/cpu/x86/lapic/lapic_cpu_init.c | 26 |
16 files changed, 66 insertions, 66 deletions
diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c index 8c1cfad..c216a81 100644 --- a/src/cpu/amd/agesa/family10/model_10_init.c +++ b/src/cpu/amd/agesa/family10/model_10_init.c @@ -61,7 +61,7 @@ static void model_10_init(device_t dev) u8 i; msr_t msr; -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS u32 siblings; #endif @@ -88,7 +88,7 @@ static void model_10_init(device_t dev) // init_processor_name(); -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c index 3a12db3..4ed477c 100644 --- a/src/cpu/amd/agesa/family12/model_12_init.c +++ b/src/cpu/amd/agesa/family12/model_12_init.c @@ -63,7 +63,7 @@ static void model_12_init(device_t dev) u8 i; msr_t msr; -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS u32 siblings; #endif @@ -94,7 +94,7 @@ static void model_12_init(device_t dev) // init_processor_name(); -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index d90695a..9cc36e2 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -61,7 +61,7 @@ static void model_14_init(device_t dev) { u32 i; msr_t msr; -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS u32 siblings; #endif printk(BIOS_DEBUG, "Model 14 Init.\n"); @@ -94,7 +94,7 @@ static void model_14_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME if (acpi_slp_type == 3) restore_mtrr(); #endif @@ -112,7 +112,7 @@ static void model_14_init(device_t dev) /* Enable the local cpu apics */ setup_lapic(); -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c index d100338..39775ba 100644 --- a/src/cpu/amd/agesa/family15/model_15_init.c +++ b/src/cpu/amd/agesa/family15/model_15_init.c @@ -59,7 +59,7 @@ static void model_15_init(device_t dev) u8 i; msr_t msr; int msrno; -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS u32 siblings; #endif @@ -95,7 +95,7 @@ static void model_15_init(device_t dev) /* Enable the local cpu apics */ setup_lapic(); -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 270c542..2aa4f30 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -29,7 +29,7 @@ static void inline __attribute__((always_inline)) memcopy(void *dest, const voi : "memory", "cc"); } -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME static inline void *backup_resume(void) { unsigned long high_ram_base; @@ -83,7 +83,7 @@ static void vErrata343(void) static void post_cache_as_ram(void) { -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME void *resume_backup_memory; #endif #if 1 @@ -108,7 +108,7 @@ static void post_cache_as_ram(void) #error "You need to set CONFIG_RAMTOP greater than 1M" #endif -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME resume_backup_memory = backup_resume(); #endif @@ -142,7 +142,7 @@ static void post_cache_as_ram(void) set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME /* now copy the rest of the area, using the WB method because we already run normal RAM */ if (resume_backup_memory) { @@ -154,7 +154,7 @@ static void post_cache_as_ram(void) print_debug("Clearing initial memory region: "); -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */ memset((void*) CONFIG_RAMBASE, 0, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE); #else diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c index 9c2583f..69ce56a 100644 --- a/src/cpu/amd/dualcore/dualcore.c +++ b/src/cpu/amd/dualcore/dualcore.c @@ -17,7 +17,7 @@ static inline unsigned get_core_num_in_bsp(unsigned nodeid) static inline uint8_t set_apicid_cpuid_lo(void) { -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT if(is_cpu_pre_e0()) return 0; // pre_e0 can not be set #endif diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index e0538af..edc016a 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -33,7 +33,7 @@ static void prep_fid_change(void); static void init_fidvid_stage2(u32 apicid, u32 nodeid); void cpuSetAMDMSR(void); -#if CONFIG_PCI_IO_CFG_EXT == 1 +#if CONFIG_PCI_IO_CFG_EXT static void set_EnableCf8ExtCfg(void) { // set the NB_CFG[46]=1; @@ -112,7 +112,7 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap, j * (nb_cfg_54 ? 1 : 64); #if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0) -#if CONFIG_LIFT_BSP_APIC_ID == 0 +#if !CONFIG_LIFT_BSP_APIC_ID if ((i != 0) || (j != 0)) /* except bsp */ #endif ap_apicid += CONFIG_APIC_ID_OFFSET; @@ -267,7 +267,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) if (id.coreid == 0) { set_apicid_cpuid_lo(); /* only set it on core0 */ set_EnableCf8ExtCfg(); /* only set it on core0 */ -#if (CONFIG_ENABLE_APIC_EXT_ID == 1) +#if CONFIG_ENABLE_APIC_EXT_ID enable_apic_ext_id(id.nodeid); #endif } @@ -277,7 +277,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) #if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0) u32 initial_apicid = get_initial_apicid(); -#if CONFIG_LIFT_BSP_APIC_ID == 0 +#if !CONFIG_LIFT_BSP_APIC_ID if (initial_apicid != 0) // other than bsp #endif { @@ -289,7 +289,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) lapic_write(LAPIC_ID, dword); } -#if CONFIG_LIFT_BSP_APIC_ID == 1 +#if CONFIG_LIFT_BSP_APIC_ID bsp_apicid += CONFIG_APIC_ID_OFFSET; #endif diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index cf11135..27f56c2 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -63,7 +63,7 @@ static void model_10xxx_init(device_t dev) u8 i; msr_t msr; struct node_core_id id; -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS u32 siblings; #endif @@ -92,7 +92,7 @@ static void model_10xxx_init(device_t dev) /* Set the processor name string */ init_processor_name(); -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 0036277..2ae9aac 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -40,7 +40,7 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap, 3); if (nb_cfg_54) { if (j == 0) { // if it is single core, we need to increase siblings for apic calculation -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT e0_later_single_core = is_e0_later_in_bsp(i); // single core #else e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 @@ -72,8 +72,8 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap, i * (nb_cfg_54 ? (siblings + 1) : 1) + j * (nb_cfg_54 ? 1 : 8); -#if (CONFIG_ENABLE_APIC_EXT_ID == 1) -#if CONFIG_LIFT_BSP_APIC_ID == 0 +#if CONFIG_ENABLE_APIC_EXT_ID +#if !CONFIG_LIFT_BSP_APIC_ID if ((i != 0) || (j != 0)) /* except bsp */ #endif ap_apicid += CONFIG_APIC_ID_OFFSET; @@ -215,7 +215,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) core0 is done at first --- use wait_all_core0_started */ if (id.coreid == 0) { set_apicid_cpuid_lo(); /* only set it on core0 */ -#if (CONFIG_ENABLE_APIC_EXT_ID == 1) +#if CONFIG_ENABLE_APIC_EXT_ID enable_apic_ext_id(id.nodeid); #endif } @@ -223,10 +223,10 @@ static u32 init_cpus(u32 cpu_init_detectedx) enable_lapic(); // init_timer(); // We need TMICT to pass msg for FID/VID change -#if (CONFIG_ENABLE_APIC_EXT_ID == 1) +#if CONFIG_ENABLE_APIC_EXT_ID u32 initial_apicid = get_initial_apicid(); -#if CONFIG_LIFT_BSP_APIC_ID == 0 +#if !CONFIG_LIFT_BSP_APIC_ID if (initial_apicid != 0) // other than bsp #endif { @@ -238,7 +238,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) lapic_write(LAPIC_ID, dword); } -#if CONFIG_LIFT_BSP_APIC_ID == 1 +#if CONFIG_LIFT_BSP_APIC_ID bsp_apicid += CONFIG_APIC_ID_OFFSET; #endif diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index ae5429d..e34e6f7 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -39,7 +39,7 @@ void cpus_ready_for_init(void) } #endif -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT int is_e0_later_in_bsp(int nodeid) { uint32_t val; @@ -67,7 +67,7 @@ int is_e0_later_in_bsp(int nodeid) } #endif -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT int is_cpu_f0_in_bsp(int nodeid) { uint32_t dword; @@ -298,7 +298,7 @@ static void init_ecc_memory(unsigned node_id) #if CONFIG_HW_MEM_HOLE_SIZEK != 0 unsigned long hole_startk = 0; -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT if (!is_cpu_pre_e0()) { #endif @@ -307,7 +307,7 @@ static void init_ecc_memory(unsigned node_id) if (val & 1) { hole_startk = ((val & (0xff << 24)) >> 10); } -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT } #endif #endif @@ -370,7 +370,7 @@ static void init_ecc_memory(unsigned node_id) static inline void k8_errata(void) { msr_t msr; -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT if (is_cpu_pre_c0()) { /* Erratum 63... */ msr = rdmsr(HWCR_MSR); @@ -437,14 +437,14 @@ static inline void k8_errata(void) #endif -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT /* I can't touch this msr on early buggy cpus */ if (!is_cpu_pre_b3()) #endif { msr = rdmsr(NB_CFG_MSR); -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT if (!is_cpu_pre_c0() && is_cpu_pre_d0()) { /* D0 later don't need it */ /* Erratum 86 Disable data masking on C0 and @@ -523,7 +523,7 @@ static void model_fxx_init(device_t dev) /* Enable the local cpu apics */ setup_lapic(); -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS u32 siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { @@ -570,7 +570,7 @@ static struct device_operations cpu_dev_ops = { }; static struct cpu_device_id cpu_table[] = { -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT { X86_VENDOR_AMD, 0xf40 }, /* SH-B0 (socket 754) */ { X86_VENDOR_AMD, 0xf50 }, /* SH-B0 (socket 940) */ { X86_VENDOR_AMD, 0xf51 }, /* SH-B3 (socket 940) */ @@ -612,7 +612,7 @@ static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0x30ff2 }, /* E4 ? */ #endif -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT /* * AMD F0 support. * diff --git a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c index 5cc0fba..69769c9 100644 --- a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c +++ b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c @@ -27,13 +27,13 @@ static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = { -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT #include "microcode_rev_c.h" #include "microcode_rev_d.h" #include "microcode_rev_e.h" #endif -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT // #include "microcode_rev_f.h" #endif /* Dummy terminator */ @@ -45,7 +45,7 @@ static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = { static unsigned get_equivalent_processor_rev_id(unsigned orig_id) { static unsigned id_mapping_table[] = { - #if CONFIG_K8_REV_F_SUPPORT == 0 + #if !CONFIG_K8_REV_F_SUPPORT 0x0f48, 0x0048, 0x0f58, 0x0048, @@ -68,7 +68,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) { 0x20fb1, 0x0210, #endif - #if CONFIG_K8_REV_F_SUPPORT == 1 + #if CONFIG_K8_REV_F_SUPPORT #endif diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c index 83d34f1..81b1067 100644 --- a/src/cpu/amd/model_fxx/powernow_acpi.c +++ b/src/cpu/amd/model_fxx/powernow_acpi.c @@ -632,7 +632,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) return 0; } -#if CONFIG_MAX_PHYSICAL_CPUS==1 +#if CONFIG_MAX_PHYSICAL_CPUS /* IRT 80us RVO = 50mV PLL_LOCK_TIME 2us, MVS 25mv, VST 100us */ control = (3 << 30) | (2 << 28) | (2 << 20) | (0 << 18) | (5 << 11); #else diff --git a/src/cpu/amd/model_fxx/processor_name.c b/src/cpu/amd/model_fxx/processor_name.c index 3f3d973..6f45b0f 100644 --- a/src/cpu/amd/model_fxx/processor_name.c +++ b/src/cpu/amd/model_fxx/processor_name.c @@ -42,7 +42,7 @@ * your mainboard will not be posted on the AMD Recommended Motherboard Website */ -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT static const char *processor_names[]={ /* 0x00 */ "AMD Engineering Sample", /* 0x01-0x03 */ NULL, NULL, NULL, @@ -113,7 +113,7 @@ static inline void wrmsr_amd(unsigned index, msr_t msr) int init_processor_name(void) { -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT u32 EightBitBrandId; #endif u32 BrandId; @@ -127,7 +127,7 @@ int init_processor_name(void) char program_string[48]; unsigned int *program_values = (unsigned int *)program_string; -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT /* Find out which CPU brand it is */ EightBitBrandId = cpuid_ebx(0x00000001) & 0xff; BrandId = cpuid_ebx(0x80000001) & 0xffff; @@ -151,7 +151,7 @@ int init_processor_name(void) processor_name_string = "AMD Processor model unknown"; #endif -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT u32 Socket; u32 CmpCap; u32 PwrLmt; @@ -407,7 +407,7 @@ int init_processor_name(void) for (i=0; i<47; i++) { // 48 -1 if(program_string[i] == program_string[i+1]) { switch (program_string[i]) { -#if CONFIG_K8_REV_F_SUPPORT == 0 +#if !CONFIG_K8_REV_F_SUPPORT case 'X': ModelNumber = 22+ NN; break; case 'Y': ModelNumber = 38 + (2*NN); break; case 'Z': @@ -416,7 +416,7 @@ int init_processor_name(void) case 'V': ModelNumber = 9 + NN; break; #endif -#if CONFIG_K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT case 'R': ModelNumber = NN - 1; break; case 'P': ModelNumber = 26 + NN; break; case 'T': ModelNumber = 15 + (CmpCap * 10) + NN; break; diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 54a70e2..5c48cfd 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -6,7 +6,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> -#if CONFIG_GFXUMA == 1 +#if CONFIG_GFXUMA extern uint64_t uma_memory_size; #endif @@ -163,7 +163,7 @@ void amd_setup_mtrrs(void) * has been deducted from the size of memory below 4GB. * When setting TOM, include UMA DRAM */ - #if CONFIG_GFXUMA == 1 + #if CONFIG_GFXUMA msr.lo += uma_memory_size; #endif wrmsr(TOP_MEM, msr); diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index e988664..2d2e105 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -7,7 +7,7 @@ #include <smp/spinlock.h> #include <assert.h> -#if CONFIG_SERIAL_CPU_INIT==0 +#if !CONFIG_SERIAL_CPU_INIT #error Intel hyper-threading requires serialized cpu init #endif diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index f823981..e491d46 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -16,7 +16,7 @@ #include <cpu/cpu.h> #include <cpu/intel/speedstep.h> -#if CONFIG_SMP == 1 +#if CONFIG_SMP /* This is a lot more paranoid now, since Linux can NOT handle * being told there is a CPU when none exists. So any errors * will return 0, meaning no CPU. @@ -29,7 +29,7 @@ static unsigned long get_valid_start_eip(unsigned long orig_start_eip) return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000 } -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME char *lowmem_backup; char *lowmem_backup_ptr; int lowmem_backup_size; @@ -49,7 +49,7 @@ static void copy_secondary_start_to_1m_below(void) start_eip = get_valid_start_eip((unsigned long)_secondary_start); code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start; -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME /* need to save it for RAM resume */ lowmem_backup_size = code_size; lowmem_backup = malloc(code_size); @@ -277,7 +277,7 @@ int start_cpu(device_t cpu) return result; } -#if CONFIG_AP_IN_SIPI_WAIT == 1 +#if CONFIG_AP_IN_SIPI_WAIT /** * Sending INIT IPI to self is equivalent of asserting #INIT with a bit of delay. @@ -384,7 +384,7 @@ static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Dat void secondary_cpu_init(void) { atomic_inc(&active_cpus); -#if CONFIG_SERIAL_CPU_INIT == 1 +#if CONFIG_SERIAL_CPU_INIT spin_lock(&start_cpu_lock); #endif @@ -399,7 +399,7 @@ void secondary_cpu_init(void) writecr4(cr4_val); #endif cpu_initialize(); -#if CONFIG_SERIAL_CPU_INIT == 1 +#if CONFIG_SERIAL_CPU_INIT spin_unlock(&start_cpu_lock); #endif @@ -417,7 +417,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) if (cpu->path.type != DEVICE_PATH_APIC) { continue; } - #if CONFIG_SERIAL_CPU_INIT == 0 + #if !CONFIG_SERIAL_CPU_INIT if(cpu==bsp_cpu) { continue; } @@ -436,7 +436,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) printk(BIOS_ERR, "CPU 0x%02x would not start!\n", cpu->path.apic.apic_id); } -#if CONFIG_SERIAL_CPU_INIT == 1 +#if CONFIG_SERIAL_CPU_INIT udelay(10); #endif } @@ -502,7 +502,7 @@ void initialize_cpus(struct bus *cpu_bus) /* Find the device structure for the boot cpu */ info->cpu = alloc_find_dev(cpu_bus, &cpu_path); -#if CONFIG_SMP == 1 +#if CONFIG_SMP copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init #endif @@ -512,8 +512,8 @@ void initialize_cpus(struct bus *cpu_bus) cpus_ready_for_init(); -#if CONFIG_SMP == 1 - #if CONFIG_SERIAL_CPU_INIT == 0 +#if CONFIG_SMP + #if !CONFIG_SERIAL_CPU_INIT /* start all aps at first, so we can init ECC all together */ start_other_cpus(cpu_bus, info->cpu); #endif @@ -522,8 +522,8 @@ void initialize_cpus(struct bus *cpu_bus) /* Initialize the bootstrap processor */ cpu_initialize(); -#if CONFIG_SMP == 1 - #if CONFIG_SERIAL_CPU_INIT == 1 +#if CONFIG_SMP + #if CONFIG_SERIAL_CPU_INIT start_other_cpus(cpu_bus, info->cpu); #endif |