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| author | Aaron Durbin <adurbin@chromium.org> | 2013-05-06 12:22:23 -0500 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-05-14 05:24:18 +0200 |
| commit | 38c326d041218e65d156ce3dd3bfee39e73ceffa (patch) | |
| tree | c48354cbb88efd809a37bb1d397ee76108ab68ec /src/cpu | |
| parent | 4409a5eef6d1d669caad1bfe3fbefee87ea7734e (diff) | |
| download | coreboot-staging-38c326d041218e65d156ce3dd3bfee39e73ceffa.zip coreboot-staging-38c326d041218e65d156ce3dd3bfee39e73ceffa.tar.gz | |
x86: add thread support
Thread support is added for the x86 architecture. Both
the local apic and the tsc udelay() functions have a
call to thread_yield_microseconds() so as to provide an
opportunity to run pending threads.
Change-Id: Ie39b9eb565eb189676c06645bdf2a8720fe0636a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3207
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/haswell/mp_init.c | 2 | ||||
| -rw-r--r-- | src/cpu/x86/lapic/apic_timer.c | 4 | ||||
| -rw-r--r-- | src/cpu/x86/lapic/lapic_cpu_init.c | 2 | ||||
| -rw-r--r-- | src/cpu/x86/tsc/delay_tsc.c | 4 |
4 files changed, 12 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c index deba629..357fbb2 100644 --- a/src/cpu/intel/haswell/mp_init.c +++ b/src/cpu/intel/haswell/mp_init.c @@ -36,6 +36,7 @@ #include <lib.h> #include <smp/atomic.h> #include <smp/spinlock.h> +#include <thread.h> #include "haswell.h" /* This needs to match the layout in the .module_parametrs section. */ @@ -163,6 +164,7 @@ static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr) info = cpu_info(); info->index = cpu; info->cpu = cpu_devs[cpu]; + thread_init_cpu_info_non_bsp(info); apic_id_table[info->index] = lapicid(); info->cpu->path.apic.apic_id = apic_id_table[info->index]; diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 749fef0..e5ce62f 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -21,6 +21,7 @@ #include <stdint.h> #include <console/console.h> #include <delay.h> +#include <thread.h> #include <arch/io.h> #include <arch/cpu.h> #include <cpu/x86/car.h> @@ -95,6 +96,9 @@ void udelay(u32 usecs) { u32 start, value, ticks; + if (!thread_yield_microseconds(usecs)) + return; + if (!timer_fsb || (lapic_read(LAPIC_LVTT) & (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) != (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 69430d5..fbc8aa4 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -32,6 +32,7 @@ #include <smp/spinlock.h> #include <cpu/cpu.h> #include <cpu/intel/speedstep.h> +#include <thread.h> #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 /* This is a lot more paranoid now, since Linux can NOT handle @@ -292,6 +293,7 @@ int start_cpu(device_t cpu) info = (struct cpu_info *)stack_end; info->index = index; info->cpu = cpu; + thread_init_cpu_info_non_bsp(info); /* Advertise the new stack and index to start_cpu */ secondary_stack = stack_end; diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 0e2a9c0..b8f2503 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -4,6 +4,7 @@ #include <cpu/x86/tsc.h> #include <smp/spinlock.h> #include <delay.h> +#include <thread.h> #if !defined(__PRE_RAM__) @@ -176,6 +177,9 @@ void udelay(unsigned us) unsigned long long current; unsigned long long clocks; + if (!thread_yield_microseconds(us)) + return; + start = rdtscll(); clocks = us; clocks *= get_clocks_per_usec(); |
