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author | Matt DeVillier <matt.devillier@gmail.com> | 2015-04-30 01:19:16 -0500 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-30 17:50:47 +0200 |
commit | 31769d99da7f97150ddc30174c7cc315ca6e7b1f (patch) | |
tree | 9ad50867ffea7f90491754e1638f3f6e4bc0241c /src/cpu | |
parent | 40e2004abf4f763f38bfb12069b683554644734a (diff) | |
download | coreboot-staging-31769d99da7f97150ddc30174c7cc315ca6e7b1f.zip coreboot-staging-31769d99da7f97150ddc30174c7cc315ca6e7b1f.tar.gz |
cpu/intel/haswell: remove dependency on socket_rpga989
Remove dependency of Haswell on cpu/intel/socket_rpga989 code,
which is a carry-over from Sandy Bridge/Ivy Bridge and older
coreboot conventions where features were structured around socket types.
Add CPU-specific options to Kconfig and required subdirs to
Makefile.inc which are curently included with socket_rpga989.
TEST=successfully built and booted on google/panther
Change-Id: Ic788e2928df107d11ea2d2eca7613490aaed395c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/10037
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu')
-rw-r--r-- | src/cpu/intel/haswell/Kconfig | 2 | ||||
-rw-r--r-- | src/cpu/intel/haswell/Makefile.inc | 8 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 741b677..00fb1d7 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -12,6 +12,8 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select BACKUP_DEFAULT_SMM_REGION select SMP + select MMX + select SSE select SSE2 select UDELAY_TSC select TSC_CONSTANT_RATE diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 82d3bec..0db0475 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -14,3 +14,11 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c smm-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc + +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../turbo |